公开(公告)号：US06444516B1

公开(公告)日：2002-09-03

申请号：US09613197

申请日：2000-07-07

Applicant: Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

Inventor： Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

IPC: H01L218234

CPC classification number: H01L21/28044 ,  H01L29/4941

Abstract: A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

Abstract translation: 用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。 栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。 栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。 调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极 门结构的传播延迟。

公开(公告)号：US06187679B1

公开(公告)日：2001-02-13

申请号：US08807739

申请日：1997-02-26

Applicant: Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

Inventor： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC: H01L2144

CPC classification number: C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

Abstract: Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

Abstract translation: 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

公开(公告)号：US5828131A

公开(公告)日：1998-10-27

申请号：US586046

申请日：1996-01-16

Applicant: Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

Inventor： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45

CPC classification number: C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

Abstract: Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.

Abstract translation: 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

公开(公告)号：US07923712B2

公开(公告)日：2011-04-12

申请号：US12492618

申请日：2009-06-26

Applicant: John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

Inventor： John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC: H01L29/02

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.

Abstract translation: PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触， 减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。

公开(公告)号：US06448173B1

公开(公告)日：2002-09-10

申请号：US09589546

申请日：2000-06-07

Applicant: Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

Inventor： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

IPC: H01L214763

CPC classification number: H01L21/76846 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

Abstract translation: 一种能够可靠地生产铝互连的双镶嵌工艺，其通过常规RIE技术生产的铝互连件具有改善的电迁移特性。 特别地，双镶嵌工艺依赖于PVD-Ti / CVD-TiN阻挡层以产生显示出显着降低的饱和电阻水平和/或抑制电迁移的铝线，特别是在长于100微米的线中。 双镶嵌铝线的电迁移寿命很大程度上取决于材料和材料填充工艺条件。 重要的是，材料和加工的偏差可导致电迁移寿命低于铝RIE互连实现的寿命。 在一个示例中，高达2.5MA / cm 2的电流密度是诱导由于电迁移引起的统计上相关的失败数量所必需的。

公开(公告)号：US5945737A

公开(公告)日：1999-08-31

申请号：US968895

申请日：1997-11-06

Applicant: Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

Inventor： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

IPC: G02B1/10 ,  C04B41/87 ,  C23C8/02 ,  C23C8/06 ,  C23C26/00 ,  C30B25/06 ,  C30B29/06 ,  C30B29/08 ,  C30B29/42 ,  C30B33/02 ,  G11B5/255 ,  G11B5/31 ,  G11B5/60 ,  G11B5/78 ,  G11B7/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/285 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/43

CPC classification number: H01L24/10 ,  C23C26/00 ,  C23C8/02 ,  G11B5/255 ,  G11B5/3106 ,  G11B5/3109 ,  G11B5/78 ,  G11B7/122 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/53204 ,  H01L24/13 ,  G11B5/313 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14

Abstract: A device having a thin film and/or a solder ball formed on a substrate. The thin film and the solder ball each include a metal and a compound that includes an oxide, nitride, or carbide precipitate of an expandable element or a contractible element. The compound is distributed in the metal to control the tensile and compressive stresses and mechanical properties of the thin film and the solder ball.

Abstract translation: 具有形成在基板上的薄膜和/或焊球的装置。 薄膜和焊球各自包括金属和包含可膨胀元件或可收缩元件的氧化物，氮化物或碳化物沉淀物的化合物。 化合物分布在金属中以控制薄膜和焊球的拉伸和压缩应力和机械性能。

公开(公告)号：US20100001253A1

公开(公告)日：2010-01-07

申请号：US12492618

申请日：2009-06-26

Applicant: John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

Inventor： John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.

Abstract translation: PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触， 减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。

公开(公告)号：US5834374A

公开(公告)日：1998-11-10

申请号：US431791

申请日：1995-05-01

Applicant: Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

Inventor： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

IPC: G02B1/10 ,  C04B41/87 ,  C23C8/02 ,  C23C8/06 ,  C23C26/00 ,  C30B25/06 ,  C30B29/06 ,  C30B29/08 ,  C30B29/42 ,  C30B33/02 ,  G11B5/255 ,  G11B5/31 ,  G11B5/60 ,  G11B5/78 ,  G11B7/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/285 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L24/10 ,  C23C26/00 ,  C23C8/02 ,  G11B5/255 ,  G11B5/3106 ,  G11B5/3109 ,  G11B5/78 ,  G11B7/122 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/53204 ,  H01L24/13 ,  G11B5/313 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14

Abstract: A method for forming thin films and controlling the tensile and compressive stresses and mechanical properties of the thin film. The method includes forming an alloy on a substrate having a solvent metal and a solute, then annealing the substrate and the alloy in one of an oxidizing, nitriding and carborizing ambient so that the ambient reacts with the solute to form respectively one of an oxide, nitride and carbide precipitates of the solute in the solvent. The solute is selected so that the precipitates formed may be used to control the mechanical properties of the solvent.

Abstract translation: 一种形成薄膜并控制薄膜的拉伸和压缩应力和机械性能的方法。 该方法包括在具有溶剂金属和溶质的基板上形成合金，然后在氧化，氮化和加硼环境中的一种中退火基板和合金，使得环境与溶质反应形成氧化物， 溶剂中溶质的氮化物和碳化物沉淀物。 选择溶质使得形成的沉淀物可用于控制溶剂的机械性能。