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    SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES
    2.
    发明申请
    SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES 失效
    半导体电容器（混合方向技术）衬底

    公开(公告)号：US20070284640A1

    公开(公告)日：2007-12-13

    申请号：US11423284

    申请日：2006-06-09

    Applicant: Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

    Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

    IPC: H01L29/94

    CPC classification number: H01L29/945 ,  H01L29/66931

    Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.

    Abstract translation: 半导体结构及其形成方法。 半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact
    4.
    发明授权
    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权
    制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法

    公开(公告)号：US06727540B2

    公开(公告)日：2004-04-27

    申请号：US10227404

    申请日：2002-08-23

    Applicant: Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    Inventor： Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    IPC: H01L27108

    CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

    Abstract: An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

    Abstract translation: 本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体 沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

    Method of simultaneously forming a line interconnect and a borderless contact to diffusion
    5.
    发明授权
    Method of simultaneously forming a line interconnect and a borderless contact to diffusion 失效
    同时形成线路互连和无边界接触到扩散的方法

    公开(公告)号：US06245651B1

    公开(公告)日：2001-06-12

    申请号：US09481916

    申请日：2000-01-12

    Applicant: Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

    Inventor： Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

    IPC: H01L213205

    CPC classification number: H01L27/10894 ,  H01L21/76802 ,  H01L27/10888

    Abstract: A method for simultaneously forming a line interconnect such as a bitline and a borderless contact to diffusion, e.g. bitline contact, is described. A semiconductor substrate having prepatterned gate stacks thereon is covered with a first dielectric to form a first level and then a second dielectric is deposited which forms a second level. Line interconnect openings are defined in the second level by lithography and etching. Etching is continued down to monocrystalline regions in an array region of the substrate to form borderless contact openings coincident to the line interconnects between the gate stacks. The openings are filled with one or more conductors to form contacts to diffusion, e.g. bitline contacts, which are coincident to the line interconnects, e.g. bitlines.

    Abstract translation: 用于同时形成诸如位线和无边界接触之类的线互连的扩散的方法，例如。 描述了位线接触。 其上具有形成图案化栅极堆叠的半导体衬底被第一电介质覆盖以形成第一电平，然后沉积形成第二电平的第二电介质。 线路互连开口通过光刻和蚀刻在第二层限定。 在衬底的阵列区域中继续蚀刻到单晶区域以形成与栅叠层之间的线互连一致的无边界接触开口。 开口填充有一个或多个导体以形成扩散接触，例如。 位线接触，其与线互连一致，例如。 位线

    Forming facet-less epitaxy with self-aligned isolation
    6.
    发明授权
    Forming facet-less epitaxy with self-aligned isolation 有权
    用自对准隔离形成无面外延

    公开(公告)号：US08969163B2

    公开(公告)日：2015-03-03

    申请号：US13556406

    申请日：2012-07-24

    Applicant: Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    Inventor： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/70

    CPC classification number: H01L21/76232 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

    Abstract translation: 形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。 第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。 第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。 使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。 沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

    Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations
    8.
    发明申请
    Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations 有权
    数字接口，用于快速，在线，统计表征过程，MOS器件和电路变化

    公开(公告)号：US20110316569A1

    公开(公告)日：2011-12-29

    申请号：US12823984

    申请日：2010-06-25

    Applicant: Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

    Inventor： Azeez Jennudin Bhavnagarwala ,  Stephen V. Kosonocky ,  Carl John Radens ,  Kevin Geoffrey Stawiasz

    IPC: G01R31/3187

    CPC classification number: G01R31/3004

    Abstract: A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of

    Abstract translation: 提供了一种用于快速准确地统计表征CMOS工艺结构，MOS器件和电路参数的电气特性变化的电路架构和方法。 所提出的电路架构和方法使得在<2mV或<1nA分辨率的测试设备的电压或电流变化的分辨率精度下<1ms / DC扫描的统计特征吞吐量。 提出的电路架构的显着特征包括一个可激励被测器件的可编程斜坡电压发生器，一个双输入9-11位循环ADC，用于捕获输入和输出来自被测器件的直流电压/电流信号，一个2 Kb的锁存器 存储器，以可编程粒度的直流扫描为每个测量点捕获9-11位流，以及时钟和控制方案，其能够连续测量和流出数字数据块，从该模块重新测量被测器件的模拟特性 。

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