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    SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP
    2.
    发明申请
    SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP 审中-公开
    多处理器芯片的功率性能优化系统

    公开(公告)号：US20090267179A1

    公开(公告)日：2009-10-29

    申请号：US12108905

    申请日：2008-04-24

    Applicant: Subramanian S. Iyer ,  Babar Ali Khan ,  Chandrasekharan Kothandaraman ,  Norman Whitelaw Robson

    Inventor： Subramanian S. Iyer ,  Babar Ali Khan ,  Chandrasekharan Kothandaraman ,  Norman Whitelaw Robson

    IPC: H01L23/525

    CPC classification number: H01L23/5256 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit.

    Abstract translation: 一个实施例中的系统包括包括多个核心的多处理器芯片; 多个电源电路，每个电源电路耦合到一个核心; 和每个电源电路中的电可编程保险丝。 每个电可编程保险丝还包括耦合到相关联的电力电路的第一电极; 耦合到相关联的电力电路的第二电极; 耦合到所述第一电极的第一焊盘; 耦合到所述第二电极的第二焊盘; 以及导电材料，其在所述第一和第二电极之间延伸并形成所述相关联的电力电路的一部分，所述导电材料的特征在于，在通过所述电极之间的施加的电流下，倾向于从所述电极之一电极转移到所述另一个电极， 其中电迁移增加了电源电路的整体电阻。

    Gas discharge lamps and lasers fabricated by micromachining methodology
    3.
    发明授权
    Gas discharge lamps and lasers fabricated by micromachining methodology 失效
    气体放电灯和激光器通过微加工方法制造

    公开(公告)号：US5955838A

    公开(公告)日：1999-09-21

    申请号：US856836

    申请日：1997-05-15

    Applicant: Babar Ali Khan ,  David A. Cammack ,  Ronald D. Pinker

    Inventor： Babar Ali Khan ,  David A. Cammack ,  Ronald D. Pinker

    IPC: G02F1/13357 ,  H01J9/26 ,  H01J61/00 ,  H01J61/30 ,  H01J61/82 ,  H01J65/00 ,  H01S3/03 ,  H01S3/097 ,  H01S3/0973 ,  H01J17/16

    CPC classification number: H01J9/261 ,  G02F1/133617 ,  H01J17/492 ,  H01J61/00 ,  H01J61/30 ,  H01J61/82 ,  H01J65/00 ,  H01J9/00 ,  H01S3/03 ,  H01S3/097 ,  H01S3/0973

    Abstract: A high pressure gas discharge lamp and the method of making same utilizing integrated circuit fabrication techniques. The lamp is manufactured from heat and pressure resistant planar substrates in which cavities are etched, by integrated circuit manufacturing techniques, so as to provide a cavity forming the gas discharge tube. Electrodes are deposited in the cavity. The cavity is filled with gas discharge materials such as mercury vapor, sodium vapor or metal halide. The substrates are bonded together and channels may be etched in the substrate so as to provide a means for connection to the electrodes. Electrodeless RF activated lamps may also be fabricated by this technique. Lamps fabricated from three or more planar substrates are disclosed.

    Abstract translation: 一种高压气体放电灯及其利用集成电路制造技术的方法。 该灯由通过集成电路制造技术蚀刻空腔的耐热和耐压平面基板制造，以提供形成气体放电管的空腔。 电极沉积在腔中。 空腔填充有气体放电材料，例如汞蒸气，钠蒸气或金属卤化物。 将基板粘合在一起，并且可以在基板中蚀刻通道，以便提供连接到电极的装置。 也可以通过这种技术制造无电极RF激活灯。 公开了由三个或更多个平面基板制造的灯。

    Method of making a channel plate for a flat display device
    4.
    发明授权
    Method of making a channel plate for a flat display device 失效
    制造平板显示装置的通道板的方法

    公开(公告)号：US5868811A

    公开(公告)日：1999-02-09

    申请号：US911080

    申请日：1997-08-14

    Applicant: Babar Ali Khan ,  Henri R. J. R. Van Helleputte ,  Adrianus L. J. Burgmans ,  Petrus F. G. Bongaerts ,  Karel Elbert Kuijk ,  Jacob Bruinink

    Inventor： Babar Ali Khan ,  Henri R. J. R. Van Helleputte ,  Adrianus L. J. Burgmans ,  Petrus F. G. Bongaerts ,  Karel Elbert Kuijk ,  Jacob Bruinink

    IPC: G02F1/1333 ,  G02F1/133 ,  G02F1/1343 ,  G09F9/35 ,  H01J9/02 ,  H01J11/02 ,  H01J17/04 ,  H01J17/16 ,  C03B23/20

    CPC classification number: G02F1/13334 ,  Y10S65/04

    Abstract: A flat display device, preferably of the PALC type, in which the plasma channels are formed by etching in a substrate laterally-spaced channels and bonding a thin dielectric sheet over the etched substrate. Adjoining each of the channels are shallow ledges, also formed by etching, which serve as recessed areas to receive enlarged ends serving as contact pads for each of the electrodes. Holes are formed in the thin dielectric sheet and contact material deposited on the bonded thin dielectric sheet such that the deposited material makes electrical contact with the underlying electrode contact pads and seals off the holes, which allows a plasma-forming atmosphere to be provided in the channels. This arrangement results in a glass-to-glass interface between the substrate and the thin dielectric sheet, which allows anodic bonding to be employed to assemble the two elements and thus eliminates the frit glass sealing process required in other constructions.

    Abstract translation: 优选为PALC型的平面显示装置，其中等离子体通道是通过在衬底中横向隔开的通道进行蚀刻而形成的，并且在蚀刻的衬底上粘合薄的电介质片。 每个通道是相邻的，也是通过蚀刻形成的浅凸缘，其用作凹陷区域以接收用作每个电极的接触焊盘的放大端。 孔形成在沉积在粘结薄电介质片上的薄电介质片和接触材料中，使得沉积的材料与下面的电极接触垫电接触并密封孔，这允许在等离子体形成气氛中提供等离子体形成气氛 频道 这种布置导致基板和薄电介质片之间的玻璃 - 玻璃界面，这允许阳极结合用于组装两个元件，从而消除了其它结构中所需的玻璃料密封过程。

    Discharge lamp with T-shaped electrodes
    7.
    发明授权
    Discharge lamp with T-shaped electrodes 失效
    放电灯带T形电极

    公开(公告)号：US5811935A

    公开(公告)日：1998-09-22

    申请号：US753546

    申请日：1996-11-26

    Applicant: Ronald D. Pinker ,  Thomas F. McGee, III ,  David Alan Cammack ,  Babar Ali Khan

    Inventor： Ronald D. Pinker ,  Thomas F. McGee, III ,  David Alan Cammack ,  Babar Ali Khan

    IPC: H01J61/06 ,  H01J17/04

    CPC classification number: H01J61/06

    Abstract: A discharge lamp includes a first and a second substrate (12, 14), a cavity disposed in the first substrate (12) or in a portion of the first and a second substrate (12, 14), a first and a second aligned electrode (270, 272) disposed between the first and a second substrate (12, 14) having respective ends extending into the cavity, wherein the first and the second aligned electrode (270, 272) are "T-shaped" when viewed in cross-section. The T-shaped electrodes provide mechanical support that minimizes bending and distortion in the horizontal and vertical directions. The discharge lamp may include a charge of mercury or an inert gas, and may further include a phosphor layer (80).

    Abstract translation: 放电灯包括第一和第二衬底（12,14），设置在第一衬底（12）中或在第一和第二衬底（12,14）的一部分中的空腔，第一和第二对齐电极 （270,272），其设置在所述第一和第二基板（12,14）之间，所述第二基板（12,14）具有延伸到所述空腔中的相应端部，其中当横截面观察时，所述第一和第二对准电极（270,272）为“T” 部分。 T形电极提供了使水平和垂直方向上的弯曲和变形最小化的机械支撑。 放电灯可以包括汞或惰性气体的电荷，并且还可以包括荧光体层（80）。

    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact
    10.
    发明授权
    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权
    制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法

    公开(公告)号：US06727540B2

    公开(公告)日：2004-04-27

    申请号：US10227404

    申请日：2002-08-23

    Applicant: Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    Inventor： Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    IPC: H01L27108

    CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

    Abstract: An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

    Abstract translation: 本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体 沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

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