公开(公告)号：US07566599B2

公开(公告)日：2009-07-28

申请号：US10996866

申请日：2004-11-24

申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

IPC分类号： H01L21/00

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US07190046B2

公开(公告)日：2007-03-13

申请号：US10708860

申请日：2004-03-29

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

IPC分类号： H01L27/082 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.

摘要翻译： 提供了用于形成双极晶体管的结构和方法。 如所公开的，提供覆盖在集电极层上的本征基层。 低电容区域横向设置在集电极层附近。 低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。 发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

公开(公告)号：US06967137B2

公开(公告)日：2005-11-22

申请号：US10604255

申请日：2003-07-07

申请人： Michael P. Belyansky ,  Rama Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

摘要： In the course of forming the collar dielectric in a DRAM cell having a deep trench capacitor, a number of filling and stripping steps required in the prior art are eliminated by the use of a spin-on material that can withstand the high temperatures required in front-end processing and also provide satisfactory filling ability and etch resistance. The use of atomic layer deposition for the formation of the collar dielectric reduces the need for a high temperature anneal of the fill material and reduces the amount of outgassing or cracking.

摘要翻译： 在具有深沟槽电容器的DRAM单元中形成环形电介质的过程中，现有技术中所需要的许多填充和剥离步骤通过使用可承受前面所需的高温的旋涂材料而消除 并且提供令人满意的填充能力和耐蚀刻性。 用于形成套环电介质的原子层沉积减少了填充材料的高温退火的需要并减少了除气或开裂的量。

公开(公告)号：US20050212087A1

公开(公告)日：2005-09-29

申请号：US10708860

申请日：2004-03-29

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/102 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.

摘要翻译： 提供了用于形成双极晶体管的结构和方法。 如所公开的，提供覆盖在集电极层上的本征基层。 低电容区域横向设置在集电极层附近。 低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。 发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

公开(公告)号：US06940149B1

公开(公告)日：2005-09-06

申请号：US10708563

申请日：2004-03-11

申请人： Rama Divakaruni ,  Gregory Freeman ,  Marwan Khater ,  William Tonti

发明人： Rama Divakaruni ,  Gregory Freeman ,  Marwan Khater ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/06 ,  H01L27/082 ,  H01L29/06 ,  H01L29/737 ,  H01L31/072

CPC分类号： H01L29/66242 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/7378

摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.

摘要翻译： 提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括 一个气隙和一个真空空隙。

公开(公告)号：US20050179112A1

公开(公告)日：2005-08-18

申请号：US11035392

申请日：2005-01-12

申请人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

发明人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

公开(公告)号：US06864540B1

公开(公告)日：2005-03-08

申请号：US10851530

申请日：2004-05-21

申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 本发明包括在绝缘体层上的场效应晶体管（FET）和包括FET的SOI芯片上的集成电路（IC）以及形成IC的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US06809368B2

公开(公告)日：2004-10-26

申请号：US09832605

申请日：2001-04-11

申请人： Rama Divakaruni ,  Thomas W. Dyer ,  Rajeev Malik ,  Jack A. Mandelman ,  Venkatachalam C. Jaiprakash

发明人： Rama Divakaruni ,  Thomas W. Dyer ,  Rajeev Malik ,  Jack A. Mandelman ,  Venkatachalam C. Jaiprakash

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L21/31612 ,  H01L21/3185 ,  H01L27/10867

摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

公开(公告)号：US06509624B1

公开(公告)日：2003-01-21

申请号：US09675246

申请日：2000-09-29

申请人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

发明人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

IPC分类号： H01L2900

CPC分类号： H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.

摘要翻译： 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括接触半导体插头的导电引线。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 每个熔丝和反熔丝都是使用一系列工艺操作来制造的，这些工序也用于根据垂直DRAM技术同时制造垂直晶体管。