公开(公告)号：US20130001660A1

公开(公告)日：2013-01-03

申请号：US13615955

申请日：2012-09-14

Applicant: Thomas W. Dyer

Inventor： Thomas W. Dyer

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

公开(公告)号：US08063449B2

公开(公告)日：2011-11-22

申请号：US12626496

申请日：2009-11-25

Applicant: Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

Inventor： Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

公开(公告)号：US07989357B2

公开(公告)日：2011-08-02

申请号：US11950741

申请日：2007-12-05

Applicant: Thomas W. Dyer ,  James J. Toomey

Inventor： Thomas W. Dyer ,  James J. Toomey

IPC: H01L23/48

CPC classification number: H01L21/8258 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/31144

Abstract: Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.

Abstract translation: 公开了图案化半导体结构的方法。 该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。 在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。 通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。 使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。 复合材料层包括在层内由直边限定的离散块中的不同材料。

公开(公告)号：US07964910B2

公开(公告)日：2011-06-21

申请号：US11873731

申请日：2007-10-17

Applicant: Thomas W. Dyer

Inventor： Thomas W. Dyer

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract translation: 公开了一种结合外延​​沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。 晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。 每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。 晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。 因此，可以通过外延沉积而不形成凹坑来填充凹部。 可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

公开(公告)号：US07863646B2

公开(公告)日：2011-01-04

申请号：US11956043

申请日：2007-12-13

Applicant: Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

Inventor： Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

IPC: H01L31/111 ,  H01L21/00

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

Abstract translation: 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

公开(公告)号：US07749903B2

公开(公告)日：2010-07-06

申请号：US12027444

申请日：2008-02-07

Applicant: Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

Inventor： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

IPC: H01L21/44

CPC classification number: H01L21/32139 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823828

Abstract: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

Abstract translation: 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

公开(公告)号：US20100148259A1

公开(公告)日：2010-06-17

申请号：US12709873

申请日：2010-02-22

Applicant: Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

Inventor： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

Abstract translation: 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US07736966B2

公开(公告)日：2010-06-15

申请号：US11968479

申请日：2008-01-02

Applicant: Thomas W. Dyer ,  Xiangdong Chen ,  James J. Toomey ,  Haining S. Yang

Inventor： Thomas W. Dyer ,  Xiangdong Chen ,  James J. Toomey ,  Haining S. Yang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/82385 ,  H01L21/823857

Abstract: The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.

Abstract translation: 本发明涉及一种制造半导体衬底的方法，该方法包括形成至少第一和第二器件区域，其中第一器件区域包括具有沿第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件 区域包括具有沿着第二不同组的等效晶面取向的内表面的第二凹部。 使用这种半导体衬底形成的半导体器件结构包括形成在第一器件区域处的至少一个n沟道场效应晶体管（n-FET），其具有沿着第一凹部的内表面延伸的沟道，并且至少一个p - 沟道场效应晶体管（p-FET），其形成在具有沿着第二凹部的内表面延伸的沟道的第二器件区域处。

公开(公告)号：US20090152638A1

公开(公告)日：2009-06-18

申请号：US11956043

申请日：2007-12-13

Applicant: MICHAEL P. BELYANSKY ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

Inventor： MICHAEL P. BELYANSKY ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

Abstract translation: 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

公开(公告)号：US07485520B2

公开(公告)日：2009-02-03

申请号：US11773607

申请日：2007-07-05

Applicant: Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

Inventor： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/785

Abstract: A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.

Abstract translation: 在半导体衬底上形成含硅翅片。 在含硅翅片的底部周围形成氧化硅层。 在含硅鳍上形成栅电介质，形成栅电极。 在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带 氧化层。 翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。 或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。