公开(公告)号：US07863646B2

公开(公告)日：2011-01-04

申请号：US11956043

申请日：2007-12-13

Applicant: Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

Inventor： Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

IPC: H01L31/111 ,  H01L21/00

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

Abstract translation: 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

公开(公告)号：US07569848B2

公开(公告)日：2009-08-04

申请号：US11362773

申请日：2006-02-28

Applicant: Michael P. Belyansky ,  Bruce B. Doris ,  Oleg G. Gluschenkov

Inventor： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg G. Gluschenkov

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

Abstract translation: 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

公开(公告)号：US20090152638A1

公开(公告)日：2009-06-18

申请号：US11956043

申请日：2007-12-13

Applicant: MICHAEL P. BELYANSKY ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

Inventor： MICHAEL P. BELYANSKY ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

Abstract translation: 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

公开(公告)号：US20080142897A1

公开(公告)日：2008-06-19

申请号：US11613149

申请日：2006-12-19

Applicant: Young Way Teh ,  Xiangdong Chen ,  Jamin F. Fen ,  Jun Jung Kim ,  Daewon Yang ,  Roman Knoefler ,  Michael P. Belyansky

Inventor： Young Way Teh ,  Xiangdong Chen ,  Jamin F. Fen ,  Jun Jung Kim ,  Daewon Yang ,  Roman Knoefler ,  Michael P. Belyansky

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.

Abstract translation: 提供了一种集成电路系统，包括在晶片上形成电路元件，在晶片上形成具有不均匀轮廓的应力形成层，并在应力形成层和晶片上形成层间电介质。

公开(公告)号：US07342266B2

公开(公告)日：2008-03-11

申请号：US11306710

申请日：2006-01-09

Applicant: Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

Inventor： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/0653 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78609 ,  Y10S438/954

Abstract: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.

Abstract translation: 场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。 在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。 在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。

公开(公告)号：US06982196B2

公开(公告)日：2006-01-03

申请号：US10605889

申请日：2003-11-04

Applicant: Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

Inventor： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

Abstract translation: 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

公开(公告)号：US07741166B2

公开(公告)日：2010-06-22

申请号：US11318818

申请日：2005-12-27

Applicant: Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

Inventor： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

Abstract: A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

Abstract translation: 提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

公开(公告)号：US07271049B2

公开(公告)日：2007-09-18

申请号：US11514605

申请日：2006-09-01

Applicant: Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

Inventor： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

IPC: H01L21/8238

CPC classification number: H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

Abstract translation: 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US06967137B2

公开(公告)日：2005-11-22

申请号：US10604255

申请日：2003-07-07

Applicant: Michael P. Belyansky ,  Rama Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

Inventor： Michael P. Belyansky ,  Rama Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

Abstract: In the course of forming the collar dielectric in a DRAM cell having a deep trench capacitor, a number of filling and stripping steps required in the prior art are eliminated by the use of a spin-on material that can withstand the high temperatures required in front-end processing and also provide satisfactory filling ability and etch resistance. The use of atomic layer deposition for the formation of the collar dielectric reduces the need for a high temperature anneal of the fill material and reduces the amount of outgassing or cracking.

Abstract translation: 在具有深沟槽电容器的DRAM单元中形成环形电介质的过程中，现有技术中所需要的许多填充和剥离步骤通过使用可承受前面所需的高温的旋涂材料而消除 并且提供令人满意的填充能力和耐蚀刻性。 用于形成套环电介质的原子层沉积减少了填充材料的高温退火的需要并减少了除气或开裂的量。

公开(公告)号：US07750410B2

公开(公告)日：2010-07-06

申请号：US11175223

申请日：2005-07-07

Applicant: Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

Inventor： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC: H01L29/72

CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Abstract translation: 在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2 ，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。