公开(公告)号：US20120027956A1

公开(公告)日：2012-02-02

申请号：US12846050

申请日：2010-07-29

Applicant: Daewon Yang ,  Anthony Gene Domenicucci ,  Aurelia Suwarno-Handayana ,  Shamas Musthafa Ummer

Inventor： Daewon Yang ,  Anthony Gene Domenicucci ,  Aurelia Suwarno-Handayana ,  Shamas Musthafa Ummer

IPC: H05H1/24 ,  C25F3/00

CPC classification number: C23C16/345 ,  C23C16/52 ,  C23C16/56

Abstract: A method of forming a nitride film is disclosed. In one embodiment, the method comprises performing an ending film deposition process that differs from the main film deposition process in terms of the flow rates of the reactive and ion source gases, and maintaining acceleration power of a CVD tool during the ending film deposition process. A post deposition process may also be used to remove a denser top layer of nitride, resulting in a nitride film having a consistent density.

Abstract translation: 公开了一种形成氮化物膜的方法。 在一个实施例中，该方法包括执行与主要成膜工艺不同的终止膜沉积工艺，就反应和离子源气体的流量而言，以及在终止膜沉积工艺期间保持CVD工具的加速能力。 后沉积工艺也可用于去除更致密的氮化物顶层，产生具有一致密度的氮化物膜。

公开(公告)号：US08030707B2

公开(公告)日：2011-10-04

申请号：US12390741

申请日：2009-02-23

Applicant: Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

Inventor： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203

Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

Abstract translation: 一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。 在结构中形成沟槽时，BOX层被切削。 该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。 间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。 还存在半导体结构，优选为SOI eDRAM结构，其具有将底切固定在BOX层中的间隔物。

公开(公告)号：US20100213522A1

公开(公告)日：2010-08-26

申请号：US12390741

申请日：2009-02-23

Applicant: Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

Inventor： Kangguo Cheng ,  Naftali Eliahu Lustig ,  Daewon Yang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203

Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

Abstract translation: 一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。 在结构中形成沟槽时，BOX层被切削。 该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。 间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。 还存在半导体结构，优选为SOI eDRAM结构，其具有将BOX层中的底切固定的间隔物。

公开(公告)号：US07750414B2

公开(公告)日：2010-07-06

申请号：US12128772

申请日：2008-05-29

Applicant: Huilong Zhu ,  Yanfeng Wang ,  Daewon Yang ,  Huajie Chen

Inventor： Huilong Zhu ,  Yanfeng Wang ,  Daewon Yang ,  Huajie Chen

IPC: H01L31/062 ,  H01L21/336

CPC classification number: H01L23/3192 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.

Abstract translation: 一种结构包括在衬底上的至少一个晶体管，晶体管上的绝缘体层，以及绝缘体层上的离子阻挡层。 离子停止层包括被破坏并具有氩离子损伤或氮离子损伤的绝缘体层的一部分。

公开(公告)号：US07521308B2

公开(公告)日：2009-04-21

申请号：US11616147

申请日：2006-12-26

Applicant: Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

Inventor： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

Abstract: A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

Abstract translation: 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

公开(公告)号：US09016236B2

公开(公告)日：2015-04-28

申请号：US12185339

申请日：2008-08-04

Applicant: Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

Inventor： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

IPC: H01L21/306 ,  C23C16/00 ,  C23C16/507 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/458 ,  C23C16/56 ,  H01J37/20 ,  H01J37/32 ,  H01L27/108 ,  H01L21/316 ,  H01L21/318

CPC classification number: C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

Abstract: A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.

Abstract translation: 公开了一种高密度等离子体化学气相沉积工具和该工具的使用方法。 化学气相沉积工具允许对保持正在制造的衬底的基座进行角度调节。 电磁铁用作允许将材料角度沉积到衬底上的“电子过滤器”。 还公开了在半导体制造工艺中制造沟槽结构和不对称间隔物的方法。 角度沉积节省了工艺步骤，从而降低了制造时间，复杂性和成本，同时提高了整体产品的产量。

公开(公告)号：US07943467B2

公开(公告)日：2011-05-17

申请号：US12016317

申请日：2008-01-18

Applicant: Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

Inventor： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract translation: 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

公开(公告)号：US20090311855A1

公开(公告)日：2009-12-17

申请号：US12544425

申请日：2009-08-20

Applicant: Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

Inventor： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC: H01L21/28

CPC classification number: H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

Abstract translation: 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US20090101980A1

公开(公告)日：2009-04-23

申请号：US11875222

申请日：2007-10-19

Applicant: Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

Inventor： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC: H01L27/088 ,  H01L21/3205

CPC classification number: H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

Abstract translation: 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US07491660B2

公开(公告)日：2009-02-17

申请号：US11873721

申请日：2007-10-17

Applicant: Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/31 ,  H01L21/469 ,  C23C16/00 ,  C23C14/10 ,  C23C14/00

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

Abstract translation: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。