Invention Grant
- Patent Title: Method of patterning semiconductor structure and structure thereof
- Patent Title (中): 图案化半导体结构及其结构的方法
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Application No.: US11950741Application Date: 2007-12-05
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Publication No.: US07989357B2Publication Date: 2011-08-02
- Inventor: Thomas W. Dyer , James J. Toomey
- Applicant: Thomas W. Dyer , James J. Toomey
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
Public/Granted literature
- US20090146221A1 METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF Public/Granted day:2009-06-11
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