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14 条记录 (耗时 0.022 秒)

    Self-aligned buried strap process using doped HDP oxide
    1.
    发明授权
    Self-aligned buried strap process using doped HDP oxide 失效
    使用掺杂HDP氧化物的自对准掩埋工艺

    公开(公告)号：US06946345B2

    公开(公告)日：2005-09-20

    申请号：US10688612

    申请日：2003-10-17

    申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L21/20

    CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

    摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

    摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

    Self aligned buried plate
    2.
    发明授权
    Self aligned buried plate 失效
    自对准埋地板

    公开(公告)号：US06699794B1

    公开(公告)日：2004-03-02

    申请号：US09037287

    申请日：1998-03-09

    申请人： Bertrand Flietner ,  Wolfgang Bergner

    发明人： Bertrand Flietner ,  Wolfgang Bergner

    IPC分类号： H01L21302

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over the polysilicon layer. After forming both the polysilicon layer and the nitride layer, both the polysilicon layer and the nitride layer are etched from a certain uppermost portion of the sidewalls of the trench thereby exposing the silicon substrate at the uppermost portions of the sidewalls. After exposing the silicon substrate at the uppermost portions of the sidewalls, a collar oxide layer is formed over the exposed silicon substrate at the uppermost portions of the sidewalls thereby protecting any edges of the polysilicon layer exposed by the etching step.

    摘要翻译： 在硅衬底中形成掩埋板的方法使用在硅衬底中蚀刻有深沟槽的硅衬底。 在沟槽内形成高度掺杂的多晶硅层。 然后在多晶硅层上的沟槽内形成氮化物层。 在形成多晶硅层和氮化物层之后，从沟槽的侧壁的特定最上部蚀刻多晶硅层和氮化物层，从而在侧壁的最上部暴露硅衬底。 在将硅衬底暴露在侧壁的最上部之后，在暴露的硅衬底上在侧壁的最上部形成环状氧化物层，从而保护通过蚀刻步骤露出的多晶硅层的任何边缘。

    Dram cell pair and dram memory cell array
    3.
    发明申请
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US20060076602A1

    公开(公告)日：2006-04-13

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L29/94 ,  H01L21/8244

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    Self-aligned buried strap process using doped HDP oxide
    5.
    发明授权
    Self-aligned buried strap process using doped HDP oxide 失效
    使用掺杂HDP氧化物的自对准掩埋工艺

    公开(公告)号：US06667504B1

    公开(公告)日：2003-12-23

    申请号：US10249228

    申请日：2003-03-24

    申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

    摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

    摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

    Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
    6.
    发明授权
    Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask 失效
    使用线位线接触掩模形成垂直DRAM阵列的位线触点的结构和方法

    公开(公告)号：US06767781B2

    公开(公告)日：2004-07-27

    申请号：US10667308

    申请日：2003-09-23

    申请人： Larry A. Nesbit ,  Jonathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

    发明人： Larry A. Nesbit ,  Jonathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

    IPC分类号： H01L218238

    CPC分类号： H01L27/10885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888

    摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

    摘要翻译： 使用位线接触掩模形成垂直DRAM阵列的位线接触的位线接触和方法。 在该方法中，形成栅极导体线。 在栅极导体线上沉积氧化物层，并且在氧化物层的部分上形成位线接触掩模。 蚀刻位线接触掩模，并且在衬底上沉积硅层。 位于硅层上的位线层被沉积。 对位线层进行掩模和蚀刻操作。 在硅层和位线（M0）层的非蚀刻部分的侧面上沉积M0金属以形成左和右位线。

    Structure and method for forming a body contact for vertical transistor cells
    7.
    发明授权
    Structure and method for forming a body contact for vertical transistor cells 失效

    公开(公告)号：US06593612B2

    公开(公告)日：2003-07-15

    申请号：US09730150

    申请日：2000-12-05

    申请人： Ulrike Gruening ,  Helmut Klose ,  Wolfgang Bergner

    发明人： Ulrike Gruening ,  Helmut Klose ,  Wolfgang Bergner

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867

    摘要： A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

    Semiconductor fuses and antifuses in vertical DRAMS
    8.
    发明授权
    Semiconductor fuses and antifuses in vertical DRAMS 有权
    垂直DRAMS中的半导体熔断器和反熔丝

    公开(公告)号：US06509624B1

    公开(公告)日：2003-01-21

    申请号：US09675246

    申请日：2000-09-29

    申请人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

    发明人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

    IPC分类号： H01L2900

    CPC分类号： H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.

    摘要翻译： 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括接触半导体插头的导电引线。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 每个熔丝和反熔丝都是使用一系列工艺操作来制造的，这些工序也用于根据垂直DRAM技术同时制造垂直晶体管。