公开(公告)号：US07393779B2

公开(公告)日：2008-07-01

申请号：US11163786

申请日：2005-10-31

Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

Abstract translation: 通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。 通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。 通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。 缩小的硬掩模然后限定通过电介质的亚光刻孔。

公开(公告)号：US5573633A

公开(公告)日：1996-11-12

申请号：US557225

申请日：1995-11-14

Applicant: Jeffrey P. Gambino ,  Mark A. Jaso ,  Larry A. Nesbit

Inventor： Jeffrey P. Gambino ,  Mark A. Jaso ,  Larry A. Nesbit

IPC: H01L21/28 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

Abstract: A method of forming interlevel studs of at least two different materials in an insulating layer on a semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias are formed through the BPSG layer in array areas. A thin doped poly layer is deposited on the surface of the BPSG layer. The structure is annealed and vias are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.

Abstract translation: 在半导体晶片上的绝缘层中形成至少两种不同材料的层间柱的方法。 在线前端（FEOL）结构上形成BPSG绝缘层后，BPSG层被化学磨光。 通过阵列区域中的BPSG层形成通孔。 在BPSG层的表面上沉积薄的掺杂多晶硅层。 结构退火，并在支撑区域形成通孔。 通过通孔将掺杂剂植入支撑区域。 在退火到漫射注入掺杂剂之后，在多层上形成金属层。 然后，该结构被化学研磨回到多层。 最终的化学抛光步骤除去多层，将金属螺柱留在支撑区域和阵列区域中的多芯金属芯柱螺柱。

公开(公告)号：US4601779A

公开(公告)日：1986-07-22

申请号：US747746

申请日：1985-06-24

Applicant: John R. Abernathey ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Thomas O. Sedgwick ,  Scott; R. Stiffler

Inventor： John R. Abernathey ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Thomas O. Sedgwick ,  Scott; R. Stiffler

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/316 ,  H01L21/2007

Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

Abstract translation: 形成半导体器件的薄硅层的形成方法。 在硅衬底上生长外延层，并且将氧或氮离子注入到外延层中以在其中形成掩埋的蚀刻停止层。 在外延层上生长氧化物层，并且用于与机械支撑晶片形成结合。 使用研磨和/或HNA去除硅衬底，使用EDP，EPP或KOH除去外延的上部，并使用非选择性蚀刻去除蚀刻停止。 外延的剩余部分形成薄硅层。 由于注入离子的均匀性，薄硅层具有非常均匀的厚度。

公开(公告)号：US4532700A

公开(公告)日：1985-08-06

申请号：US604563

申请日：1984-04-27

Applicant: Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

Inventor： Wayne I. Kinney ,  Jerome B. Lasky ,  Larry A. Nesbit

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide having a predetermined thickness.

Abstract translation: 提供了一种用于制造在硅体一侧具有介电隔离的硅区的半导体结构的方法。 这通过在硅体中形成一组掩埋区域和具有使其阳极蚀刻比硅体的剩余部分更慢的特性的一组表面区域来实现。 这两组区域限定了硅体中的阳极蚀刻部分以形成多孔硅区域，这些硅区域被氧化以形成将硅表面区域与硅体的其余部分隔离的隔离结构。 通常在P型硅体中，掩埋和表面区域是通过离子注入形成的N型区域。 使用这些N型区域来控制P型材料暴露于阳极蚀刻溶液和形成多孔硅区域，获得的结构是其中表面单晶硅区域与硅体的其余部分通过 均匀的具有预定厚度的二氧化硅层。

公开(公告)号：US20090014767A1

公开(公告)日：2009-01-15

申请号：US10596022

申请日：2003-12-18

Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC: H01L27/108

CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract translation: 沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成在沟槽内衬的开放圆筒结构。 该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

公开(公告)号：US07187085B2

公开(公告)日：2007-03-06

申请号：US10853492

申请日：2004-05-26

Applicant: Lawrence A. Clevenger ,  Larry A. Nesbit

Inventor： Lawrence A. Clevenger ,  Larry A. Nesbit

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.

Abstract translation: 在半导体衬底上形成互连的方法（和结构）包括在形成在半导体衬底上的电介质中形成相对窄的第一结构，在形成在半导体衬底上的电介质中形成相对较宽的第二结构， 所述第一和第二结构使得所述第一结构基本上被填充并且所述第二结构基本上未被填充，并且在所述衬套上形成金属化以完全填充所述第二结构。

公开(公告)号：US06686668B2

公开(公告)日：2004-02-03

申请号：US09764833

申请日：2001-01-17

Applicant: Larry A. Nesbit ,  Johnathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

Inventor： Larry A. Nesbit ,  Johnathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

IPC: H01L27108

CPC classification number: H01L27/10885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

公开(公告)号：US4558508A

公开(公告)日：1985-12-17

申请号：US660673

申请日：1984-10-15

Applicant: Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

Inventor： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/76218 ,  H01L21/033 ,  H01L21/823892 ,  H01L29/0638 ,  H01L27/0928 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/10 ,  Y10S148/157

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

Abstract translation: 制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。 光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体） 在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。 结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。 然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。

公开(公告)号：US4389257A

公开(公告)日：1983-06-21

申请号：US288608

申请日：1981-07-30

Applicant: Henry J. Geipel, Jr. ,  Ning Hsieh ,  Charles W. Koburger, III ,  Larry A. Nesbit

Inventor： Henry J. Geipel, Jr. ,  Ning Hsieh ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/285

CPC classification number: H01L29/4975 ,  H01L21/28061 ,  H01L21/321 ,  H01L21/76889 ,  Y10S148/147

Abstract: A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

Abstract translation: 一种提供半导体器件的自钝化互连电极的方法，其提供低电阻率复合多硅化物电极。 在该方法中，通过沉积多晶硅和化学计量比例的硅和形成硅化物的金属来消除在硅化物下面的多晶硅中形成氧化诱发的空隙。 这些步骤之后是沉积具有确定提供形成二氧化硅钝化层所需的硅的30％至100％的厚度的硅层。 层状电极结构的随后的热氧化提供了用于制造硅栅极MOSFET器件以及其它集成电路结构的自钝化结构。

公开(公告)号：US07250347B2

公开(公告)日：2007-07-31

申请号：US10905979

申请日：2005-01-28

Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

Abstract translation: 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。