公开(公告)号：US06335272B1

公开(公告)日：2002-01-01

申请号：US09637935

申请日：2000-08-14

Applicant: Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

Inventor： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

IPC: H01L214763

CPC classification number: H01L21/28512 ,  H01L21/28518 ,  H01L21/28568

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

Abstract translation: 提供了一种用于其制造的埋地对接接触和方法，其包括具有第一导电类型的掺杂剂并且具有浅沟槽隔离的衬底。 第二导电类型的掺杂剂位于所述衬底中的开口的底部。 在衬底中的掺杂剂和位于开口的侧壁上的低扩散性掺杂剂之间提供欧姆接触。 接触是金属硅化物，金属和/或金属合金。

公开(公告)号：US4558508A

公开(公告)日：1985-12-17

申请号：US660673

申请日：1984-10-15

Applicant: Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

Inventor： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/76218 ,  H01L21/033 ,  H01L21/823892 ,  H01L29/0638 ,  H01L27/0928 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/10 ,  Y10S148/157

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

Abstract translation: 制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。 光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体） 在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。 结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。 然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。

公开(公告)号：US4470189A

公开(公告)日：1984-09-11

申请号：US497372

申请日：1983-05-23

Applicant: Stanley Roberts ,  Francis R. White

Inventor： Stanley Roberts ,  Francis R. White

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/283 ,  C23C15/00

CPC classification number: H01L29/66575 ,  H01L21/0272 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/7688 ,  H01L21/76889 ,  Y10S148/084 ,  Y10S438/951

Abstract: An improved method for making polycide structures for use in electrode and wiring interconnection applications. It includes depositing a layer of polysilicon on an insulating layer and forming on this polysilicon layer a silicide structure and a silicon capping layer. The deposited layers are defined and etched through dry etching techniques using a dry etching mask made of a refractory metal that does not form a volatile halide in a dry etching environment. Metals with such characteristics include cobalt (Co), nickel (Ni), iron (Fe), and manganese (Mn). The metal mask and the other deposited layers may be formed and defined using a photoresist mask as a deposition mask formed to be compatible with lift-off techniques.The silicide may be deposited either through a chemical vapor deposition process or through evaporation techniques. If it is formed through the co-evaporation of metal and silicon, then the structure is subjected to a low temperature reaction annealing step at a temperature between 500.degree. and 600.degree. C. prior to dry etching. To avoid a diffusion of the metal mask into the silicon layer, during this low temperature annealing, the process provides for the formation of a diffusion barrier layer between the metal mask and the silicon layer.Following the removal of the metal mask and the diffusion barrier layer, the structure is annealed at a temperature sufficient to cause the homogenization of the silicide layer.

Abstract translation: 一种用于制造用于电极和布线互连应用的多晶硅结构的改进方法。 它包括在绝缘层上沉积多晶硅层，并在该多晶硅层上形成硅化物结构和硅覆盖层。 通过干法蚀刻技术，使用由干蚀刻环境中不形成挥发性卤化物的难熔金属制成的干蚀刻掩模来定义和蚀刻沉积层。 具有这种特性的金属包括钴（Co），镍（Ni），铁（Fe）和锰（Mn）。 可以使用形成为与剥离技术相容的沉积掩模的光致抗蚀剂掩模来形成和限定金属掩模和其它沉积层。 硅化物可以通过化学气相沉积工艺或通过蒸发技术沉积。 如果通过金属和硅的共蒸发形成，则在干蚀刻之前，在500℃和600℃之间的温度下对该结构进行低温反应退火步骤。 为了避免金属掩模扩散到硅层中，在该低温退火期间，该工艺提供了在金属掩模和硅层之间形成扩散阻挡层。 在除去金属掩模和扩散阻挡层之后，该结构在足以使硅化物层均匀化的温度下退火。

公开(公告)号：US06038168A

公开(公告)日：2000-03-14

申请号：US105339

申请日：1998-06-26

Applicant: Archibald J. Allen ,  Jerome B. Lasky ,  John J. Pekarik ,  Jed H. Rankin ,  Francis R. White

Inventor： Archibald J. Allen ,  Jerome B. Lasky ,  John J. Pekarik ,  Jed H. Rankin ,  Francis R. White

IPC: G11C17/16 ,  G11C17/18 ,  G11C7/00

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: A method and apparatus for conditioning an integrated circuit to always enter a desired operating state when actuated by permanently altering at least one component device. An integrated circuit is provided with at least one component transistor wherein a constant high voltage is applied only once to the drain electrode of the transistor for one predetermined period of time while concurrently a constant voltage lower than the high voltage is applied only once to the gate electrode of the transistor, thus causing a permanent channel hot-electron alteration of a gate oxide of the transistor. The integrated circuit may include a plurality of programmable circuits, each capable of assuming a plurality of readable data states when powered up, and each including a plurality of programmable devices for permanently biasing its corresponding programmable circuit to assume one of the readable states upon subsequent power ups.

Abstract translation: 一种用于调节集成电路以在通过永久地改变至少一个组件装置致动时始终进入期望操作状态的方法和装置。 集成电路设置有至少一个元件晶体管，其中恒定的高电压仅施加一次到晶体管的漏极一个预定时间段，同时将低于高电压的恒定电压仅施加一次到栅极 电极，从而导致晶体管的栅极氧化物的永久性通道热电子改变。 集成电路可以包括多个可编程电路，每个可编程电路能够在通电时呈现多个可读数据状态，并且每个可编程电路包括多个可编程器件，用于永久地偏置其相应的可编程电路，以在后续电源中呈现可读状态之一 UPS。

公开(公告)号：US5270261A

公开(公告)日：1993-12-14

申请号：US965728

申请日：1992-10-23

Applicant: Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Willem B. van der Hoeven ,  Francis R. White

Inventor： Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Willem B. van der Hoeven ,  Francis R. White

IPC: H01L25/065 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  Y10S148/135

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having high aspect ratio metallized trenches therein extending from a first surface to a second surface thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate. Next the integrated circuit device is affixed to a carrier such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches. Specific details of the fabrication method and the resultant multichip package are set forth.

Abstract translation: 公开了一种具有通过多个金属化沟槽至少部分互连的半导体芯片的密集堆叠阵列的制造方法和所得的三维多芯片封装。 制造方法包括提供其中从其第一表面延伸到其第二表面的具有高纵横比金属化沟槽的集成电路芯片。 在具有半导体衬底的金属化沟槽的终止位置附近提供蚀刻停止层。 接下来，集成电路器件被固定到载体上，使得支撑衬底的表面被暴露，并且衬底从集成电路器件变薄，直到暴露其中的多个金属化沟槽中的至少一些。 因此，可以通过暴露的金属化沟槽对集成电路芯片的有源层进行电接触。 阐述制造方法和所得多芯片封装的具体细节。

公开(公告)号：US5055898A

公开(公告)日：1991-10-08

申请号：US693880

申请日：1991-04-30

Applicant: Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John R. Pessetto ,  Francis R. White

Inventor： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John R. Pessetto ,  Francis R. White

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/10 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10844 ,  H01L27/10832 ,  H01L29/78603 ,  H01L29/78654

Abstract: A semiconductor memory cell, and methods of fabricating same, that includes a substrate (10) and a plurality of trench capacitors (12) formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator (SOI) region includes a silicon layer (16) that overlies an insulator (14). The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline (20), for forming a gate node of an access transistor (1), to a second electrode, or bitline (32), for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure (11, 13) for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.

Abstract translation: 一种半导体存储单元及其制造方法，其包括基板（10）和至少部分地形成在基板内并与之介电隔离的多个沟槽电容器（12）。 绝缘体上硅（SOI）区域包括覆盖绝缘体（14）的硅层（16）。 硅层被区分成多个有源器件区域，每个有源器件区域设置在一个导电区域之上。 每个有源器件区域耦合到上覆的第一电极或用于形成存取晶体管（1）的栅极节点的字线（20），到第二电极或位线（32），用于形成源节点 存取晶体管，以及用于形成存取晶体管的漏极节点的底层沟槽电容器。 字线包括一对相对的，电绝缘的垂直侧壁，并且每个存取晶体管的源极节点和漏极节点各自包括设置在垂直侧壁中的一个上的电导体。 存储单元阵列还包括用于将有源器件区域耦合到衬底的结构（11,13），以减少或消除浮置衬底效应。

公开(公告)号：US08133772B2

公开(公告)日：2012-03-13

申请号：US13075271

申请日：2011-03-30

Applicant: John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

Inventor： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

IPC: H01L21/8242

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

Abstract translation: 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

公开(公告)号：US6153934A

公开(公告)日：2000-11-28

申请号：US126577

申请日：1998-07-30

Applicant: Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

Inventor： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

IPC: H01L21/28 ,  H01L21/285 ,  H01L23/48

CPC classification number: H01L21/28512 ,  H01L21/28518 ,  H01L21/28568

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

公开(公告)号：US4799990A

公开(公告)日：1989-01-24

申请号：US44374

申请日：1987-04-30

Applicant: Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

Inventor： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/76224

Abstract: A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

公开(公告)号：US4527325A

公开(公告)日：1985-07-09

申请号：US564880

申请日：1983-12-23

Applicant: Henry J. Geipel, Jr. ,  Charles A. Schaefer ,  Francis R. White ,  John M. Wursthorn

Inventor： Henry J. Geipel, Jr. ,  Charles A. Schaefer ,  Francis R. White ,  John M. Wursthorn

IPC: H01L21/22 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/321 ,  H01L21/324 ,  H01L21/265 ,  H01L21/31

CPC classification number: H01L21/324 ,  H01L21/3145 ,  H01L21/32105 ,  Y10S438/911

Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.

Abstract translation: 提供了一种用于制造半导体结构的方法，其中该结构必须在其某些处理步骤中暴露于某些氧化条件，例如其在氧化环境中的高温退火。 其包括沉积诸如硅的“牺牲”层，以在随后的退火操作期间提供均匀氧化的表面。 这种氧化均匀的牺牲层产生也均匀蚀刻的氧化物层。 因此，退火完成后，通过蚀刻去除表面氧化物，然后通过不同的蚀刻步骤除去牺牲层。