公开(公告)号：US08877596B2

公开(公告)日：2014-11-04

申请号：US12822426

申请日：2010-06-24

Applicant: Darshana N. Bhagat ,  Thomas J. Dunbar ,  Yen Li Lim ,  Jed H. Rankin ,  Eva A. Shah

Inventor： Darshana N. Bhagat ,  Thomas J. Dunbar ,  Yen Li Lim ,  Jed H. Rankin ,  Eva A. Shah

IPC: H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823807 ,  H01L29/7833

Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.

Abstract translation: 一种方法包括在一个或多个栅极结构上形成硬掩模。 该方法还包括在硬掩模上形成光致抗蚀剂。 该方法还包括在至少一个栅极结构上的光致抗蚀剂中形成开口。 该方法还包括剥离暴露在开口中且位于至少一个栅极结构之上的硬掩模。 该方法还包括去除光致抗蚀剂。 该方法还包括在所述至少一个栅极结构的一侧上提供晕轮植入物。

公开(公告)号：US08815671B2

公开(公告)日：2014-08-26

申请号：US12892474

申请日：2010-09-28

Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

Abstract translation: 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

公开(公告)号：US08609453B2

公开(公告)日：2013-12-17

申请号：US12951601

申请日：2010-11-22

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/00

CPC classification number: H01L31/186 ,  H01L31/0248 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.

Abstract translation: 描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。 形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。 该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。

公开(公告)号：US20130170012A1

公开(公告)日：2013-07-04

申请号：US13343395

申请日：2012-01-04

Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B26/00

CPC classification number: G02B26/0841 ,  G02B5/201

Abstract: Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors.

Abstract translation: 直观视图彩色显示器和直观视图彩色显示器的设计结构。 直视图显示器包括具有不倾斜和倾斜状态的微镜，以及多个滤色器或彩色反射器。

公开(公告)号：US08445965B2

公开(公告)日：2013-05-21

申请号：US12940115

申请日：2010-11-05

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

Abstract translation: 一种制造结构的结构和方法。 该结构包括半导体衬底的第一区域，其通过在衬底中形成的沟槽隔离与半导体衬底的第二区域分离; 第一个区域的第一个应力层; 在第二区域的第二个应力层; 第一应力层和第二应力层由间隙分开; 以及在第一和第二应力层上的钝化层，钝化层延伸并密封间隙。

公开(公告)号：US20130065370A1

公开(公告)日：2013-03-14

申请号：US13229154

申请日：2011-09-09

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/785

Abstract: A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.

Abstract translation: 在衬底上形成特征的方法包括在衬底上形成至少一层特征材料，在特征材料的至少一层上图案化光刻抗蚀剂材料，去除特征材料的部分以限定特征，沉积 在抗蚀剂材料上的掩模材料层和衬底的暴露区域，修改衬底的一部分，以及去除掩模材料层和抗蚀剂材料。

公开(公告)号：US08389183B2

公开(公告)日：2013-03-05

申请号：US12702787

申请日：2010-02-09

Applicant: Brent A. Anderson ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Jed H. Rankin

IPC: G03F1/28 ,  G03F1/29 ,  G03F1/34

CPC classification number: G03F1/29 ,  G03F1/34

Abstract: A phase-shifting photomask with a self aligned undercut rim-shifting element and methods for its manufacture are provided. One embodiment of the invention provides a method of manufacturing a phase-shifting photomask having a self aligned rim-shifting element, the method comprising: applying a patterning film to a first portion of a transparent substrate; etching the substrate to a depth to remove a second portion of the substrate not beneath the patterning film; etching the first portion of the substrate to undercut an area beneath the patterning film; and removing the patterning film, wherein the etched substrate forms a self-aligned undercut rim-shifting element.

Abstract translation: 提供了具有自对准底切边缘移动元件的相移光掩模及其制造方法。 本发明的一个实施例提供了一种制造具有自对准边缘移位元件的相移光掩模的方法，所述方法包括：将图案化膜施加到透明基板的第一部分; 将衬底蚀刻到深度以去除衬底的第二部分而不在图案化膜下方; 蚀刻基板的第一部分以削去图案化膜下方的区域; 并且去除所述图案化膜，其中所述蚀刻的衬底形成自对准底切轮辋移位元件。

公开(公告)号：US08216909B2

公开(公告)日：2012-07-10

申请号：US12547529

申请日：2009-08-26

Applicant: Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

Inventor： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

Abstract translation: 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US20120098066A1

公开(公告)日：2012-04-26

申请号：US12909917

申请日：2010-10-22

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L29/7855 ,  H01L21/3081 ,  H01L29/66795 ,  H01L29/785

Abstract: A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure.

Abstract translation: 一种方法和结构包括场效应晶体管结构，其包括在衬底上的第一矩形鳍结构位置。 第一矩形翅片结构具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。 该结构还包括在基底上的第二矩形翅片结构位置。 类似地，第二矩形翅片结构还具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。 第二矩形翅片结构的侧面平行于第一矩形翅片结构的侧面。 此外，沟槽绝缘体位于衬底上并且位于第一矩形翅片结构的侧面和第二矩形鳍结构的侧面之间。 此外，栅极导体位于沟槽绝缘体上，位于第一矩形翅片结构的侧面和顶部之上，并且位于第二矩形鳍结构的侧面和顶部之上。 栅极导体垂直于第一矩形翅片结构的侧面和第二矩形翅片结构的侧面延伸。 此外，栅极绝缘体位于栅极导体和第一矩形翅片结构之间以及栅极导体和第二矩形鳍结构之间。 该结构还包括在第一矩形翅片结构的顶部上的第一盖。 第一盖将栅极导体与第一矩形鳍结构分开。

公开(公告)号：US20120074502A1

公开(公告)日：2012-03-29

申请号：US12892474

申请日：2010-09-28

Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

IPC: H01L25/11 ,  H01L21/77

CPC classification number: H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

Abstract translation: 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。