公开(公告)号：US20060289909A1

公开(公告)日：2006-12-28

申请号：US11514605

申请日：2006-09-01

申请人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

发明人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

IPC分类号： H01L29/76

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US20080042174A1

公开(公告)日：2008-02-21

申请号：US11923075

申请日：2007-10-24

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

公开(公告)号：US07273638B2

公开(公告)日：2007-09-25

申请号：US10338254

申请日：2003-01-07

申请人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

发明人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

IPC分类号： H05H1/46 ,  B05D3/06 ,  B05D3/14 ,  C23C16/40 ,  C23C16/505 ,  H01L21/473 ,  C23C16/509

CPC分类号： H01L21/31658 ,  C23C8/36 ,  H01J37/321 ,  H01J2237/338 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662

摘要： A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm−3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

摘要翻译： 一种氧化具有约30,000mm 2以上面积的基材的方法。 该表面优选由含硅材料，例如硅，硅锗，碳化硅，氮化硅和金属硅化物组成。 通常对氧气（例如Ne，Ar，Kr，Xe和/或Rn）通常不与氧反应的含氧气体和稀释气体的混合物被电离以产生电子密度为至少约1e12cm -3，并且包含平均温度大于约1eV的环境电子。 衬底表面被能量粒子氧化，主要由等离子体中产生的原子氧组成，形成厚度基本均匀的氧化膜。 衬底的氧化在低于约700℃的温度下进行，例如在约室温，20℃和约500℃之间。

公开(公告)号：US20070010070A1

公开(公告)日：2007-01-11

申请号：US11160668

申请日：2005-07-05

申请人： Michael Belyansky ,  Meikei Ieong ,  Haizhou Yin

发明人： Michael Belyansky ,  Meikei Ieong ,  Haizhou Yin

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76254

摘要： The present invention relates to a method for forming one or more strained semiconductor-on-insulator structures, by first forming a precursor structure that contains an upper layer of unstrained semiconductor material and a lower layer of strained insulating material supported by a semiconductor substrate, and then patterning the upper layer of unstrained semiconductor material and the lower layer of strained insulating material to form one or more islands that each contain an unstrained semiconductor material layer over a strained insulating material layer. Relaxation of the strained insulating material layers in such islands applies strain to the unstrained semiconductor material layers, thus forming one or more strained semiconductor-on-insulator structures. The method of the present invention uses a strained insulating material layer to apply strain to an unstrained semiconductor material layer, and can therefore completely avoid usage of any additional strain-inducing layer in forming strained semiconductor material.

摘要翻译： 本发明涉及一种用于形成一个或多个应变的绝缘体上半导体结构的方法，首先形成一个前体结构，该前体结构含有一个上层的无约束半导体材料和一个由半导体衬底支撑的应变绝缘材料层， 然后对未应变半导体材料的上层和应变绝缘材料的下层进行构图，以形成一个或多个岛，每个岛在应变绝缘材料层上都包含未应变的半导体材料层。 这种岛中的应变绝缘材料层的松弛对未受约束的半导体材料层施加应变，从而形成一个或多个应变绝缘体上的半导体结构。 本发明的方法使用应变绝缘材料层将应变施加到未应变半导体材料层，因此可以完全避免在形成应变半导体材料时使用任何额外的应变诱导层。

公开(公告)号：US20060131659A1

公开(公告)日：2006-06-22

申请号：US11318844

申请日：2005-12-27

申请人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

公开(公告)号：US20060099783A1

公开(公告)日：2006-05-11

申请号：US10904391

申请日：2004-11-08

申请人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

发明人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

IPC分类号： H01L21/3205

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located atop a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面上方的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US20050260819A1

公开(公告)日：2005-11-24

申请号：US10709652

申请日：2004-05-20

申请人： Michael Belyansky ,  Joyce Liu ,  Hsing Jen Wann ,  Richard Wise ,  Hongwen Yan

发明人： Michael Belyansky ,  Joyce Liu ,  Hsing Jen Wann ,  Richard Wise ,  Hongwen Yan

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.

摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。 栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。 优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。 间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。 间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。 可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

公开(公告)号：US20050179112A1

公开(公告)日：2005-08-18

申请号：US11035392

申请日：2005-01-12

申请人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

发明人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

公开(公告)号：US20070245957A1

公开(公告)日：2007-10-25

申请号：US11769372

申请日：2007-06-27

申请人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

发明人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

IPC分类号： C23C16/00

CPC分类号： H01L21/31658 ,  C23C8/36 ,  H01J37/321 ,  H01J2237/338 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662

摘要： A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal silicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1 e12 cm−3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

摘要翻译： 一种氧化具有约30,000mm 2以上面积的基材的方法。 表面优选由含硅材料，例如硅，硅锗，碳化硅，氮化硅和金属硅化物组成。 通常对氧气，例如Ne，Ar，Kr，Xe和/或Rn不反应的含氧气体和稀释剂气体的混合物被电离以产生电子密度为至少约1×12cm× > -3，并且包含平均温度大于约1eV的环境电子。 衬底表面被能量粒子氧化，主要由等离子体中产生的原子氧组成，形成厚度基本均匀的氧化膜。 衬底的氧化在低于约700℃的温度下进行，例如在约室温，20℃和约500℃之间。

公开(公告)号：US20070063277A1

公开(公告)日：2007-03-22

申请号：US11162778

申请日：2005-09-22

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.

摘要翻译： 本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极 氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。