公开(公告)号：US20050186788A1

公开(公告)日：2005-08-25

申请号：US11090103

申请日：2005-03-24

Applicant: Jiong-Ping Lu ,  Qi-Zhong Hong ,  Tz-Cheng Chiu ,  Changming Jin ,  David Permana ,  Ting Tsui

Inventor： Jiong-Ping Lu ,  Qi-Zhong Hong ,  Tz-Cheng Chiu ,  Changming Jin ,  David Permana ,  Ting Tsui

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76834 ,  H01L21/76877 ,  H01L21/76883

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

公开(公告)号：US06835648B2

公开(公告)日：2004-12-28

申请号：US10448097

申请日：2003-05-29

Applicant: Qi-Zhong Hong ,  Peter Huang

Inventor： Qi-Zhong Hong ,  Peter Huang

IPC: H01L214763

CPC classification number: H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.

Abstract translation: 本发明的实施例是制造半导体晶片2的方法，其中在前端结构3上形成未掺杂的硅玻璃15层。本发明的另一个实施例是具有后端结构4的集成电路2 其中介电层15包含未掺杂的硅玻璃。

公开(公告)号：US06544886B2

公开(公告)日：2003-04-08

申请号：US09574731

申请日：2000-05-18

Applicant: Jiong-Ping Lu ,  Qi-Zhong Hong ,  Duane E. Carter ,  Yung Liu

Inventor： Jiong-Ping Lu ,  Qi-Zhong Hong ,  Duane E. Carter ,  Yung Liu

IPC: H01L214763

CPC classification number: H01L21/02244 ,  H01L21/02178 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28562 ,  H01L21/31683 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76888

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

公开(公告)号：US06461955B1

公开(公告)日：2002-10-08

申请号：US09521325

申请日：2000-03-09

Applicant: Robert Tsu ,  Qi-Zhong Hong ,  William R. Mckee

Inventor： Robert Tsu ,  Qi-Zhong Hong ,  William R. Mckee

IPC: H01L214763

CPC classification number: H01L21/76808 ,  H01L21/76805

Abstract: A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).

Abstract translation: 双镶嵌工艺。 在通孔蚀刻之后，通孔保护层（114）沉积在通孔（112）中。 通孔保护层（114）包括具有至少等于IMD（108）的干蚀刻速率的干蚀刻速率和大约为IMD（108）或更大的100倍的湿蚀刻速率的材料。 示例性材料包括PSG，BPSG和HSQ。 形成沟槽图案（120）并蚀刻通孔保护层（114）和IMD（108）。 然后在形成金属层（122）之前去除通孔保护层（114）的剩余部分。

公开(公告)号：US06372566B1

公开(公告)日：2002-04-16

申请号：US09110034

申请日：1998-07-02

Applicant: Jorge A. Kittl ,  Qi-Zhong Hong

Inventor： Jorge A. Kittl ,  Qi-Zhong Hong

IPC: H01L218238

CPC classification number: H01L21/28052 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/665

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof. The metal layer is, preferably, comprised of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.

Abstract translation: 本发明的一个实施例是制造具有绝缘地设置在半导体衬底上的硅化栅结构的晶体管的方法，该方法包括以下步骤：形成绝缘地设置在半导体衬底上的导电结构（图3的步骤302） ; 将硅化物增强物质引入导电结构体（图3的步骤304）; 导电结构的一部分非晶化; 在导电结构上形成金属层（图3的步骤310）; 并且其中所述金属层与所述导电结构的非晶化部分中的所述硅化物增强物质相互作用，以便在所述导电结构上形成较低电阻率的硅化物。 导电结构优选地包括：掺杂多晶硅，未掺杂多晶硅，外延硅或其任何组合。 优选地，硅化物增强物质包括：钼，钴，钨，钽，铌，钌，铬，任何难熔金属及其任何组合。 金属层优选由钛，钴，钨，钼，镍，铂，钯及其任何组合组成。

公开(公告)号：US06245672B1

公开(公告)日：2001-06-12

申请号：US09177412

申请日：1998-10-23

Applicant: Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

Inventor： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

IPC: H01L214763

CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76855

Abstract: An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.

Abstract translation: 公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。 该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。 在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层 铜金属化（20,32,42）。 化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

公开(公告)号：US6150252A

公开(公告)日：2000-11-21

申请号：US654810

申请日：1996-05-29

Applicant: Wei-Yung Hsu ,  Qi-Zhong Hong

Inventor： Wei-Yung Hsu ,  Qi-Zhong Hong

IPC: H01L21/283 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76858 ,  H01L21/76843 ,  H01L21/76877

Abstract: Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity at a relatively low power and deposition rate to enhance "wetting" of a subsequently deposited fill material. The fill material is deposited at a comparatively greater power and deposition rate to close the mouth of the cavity, after which the fill material is extruded at high pressure into the cavity to substantially fill the cavity. Relatively low processing temperatures and high pressures are utilized to allow for the use of lower dielectric constant dielectrics, which are thermally unstable at conventional processing temperatures.

Abstract translation: 诸如在半导体器件中形成的通孔和触点的腔被填充在多级工艺中以提供低电阻电连接。 首先以相对低的功率和沉积速率将衬垫沉积到腔中，以增强随后沉积的填充材料的“润湿”。 填充材料以相对较大的功率和沉积速率沉积以封闭空腔的口部，然后将填充材料以高压挤出到空腔中以基本上填充空腔。 使用相对低的加工温度和高压力来允许使用在常规加工温度下热不稳定的较低介电常数电介质。

公开(公告)号：US6048784A

公开(公告)日：2000-04-11

申请号：US212189

申请日：1998-12-15

Applicant: Qi-Zhong Hong ,  Jorge A. Kittl

Inventor： Qi-Zhong Hong ,  Jorge A. Kittl

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/477

CPC classification number: H01L29/665 ,  H01L21/26586 ,  H01L21/28052 ,  H01L29/4941 ,  H01L21/26506

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract translation: 提供一种制造具有改进的浸水栅的晶体管的方法。 该方法可以包括形成通过栅极绝缘体（16）与衬底（12）分离的栅极（14）。 可以在栅极（14）附近形成间隔物（22），使得间隔物（22）暴露栅极（14）的顶部区域（28）和侧部区域（30）。 可以以角度（38）照射栅极（14）的顶部区域（28）和侧部区域（30），以在栅极（14）内形成柱状非晶区域（32）。 可以在后非晶区域（32）附近形成反应层（42）。 然后可以在后非晶态区域（32）和反应层（42）之间形成水化区域（44）。 可以除去反应层（42）以暴露出盐化区域（44）。

公开(公告)号：US5985763A

公开(公告)日：1999-11-16

申请号：US970961

申请日：1997-11-14

Applicant: Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

Inventor： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

Abstract translation: 提供了用于在诸如半导体器件的结构中的非相邻层之间的金属 - 金属连接的构造的方法。 沿着基板设置第一金属导体层。 防反射盖以与所述第一导体层重叠的关系提供。 去除介电层和防反射盖的至少一部分以限定从电介质层的上表面延伸到第一金属导体的通道。 通道基本上填充有填充金属，并且第二金属导体层被施加在电介质层和基本上填充的通道的至少一部分上以电连接第一和第二金属导体。 在施加填充金属之前，扩散衬垫可以可选地施加到通道。 通道填充金属和第二导体层可以一体地形成，并且填充金属和至少一个导体层由相同的基体金属形成。

公开(公告)号：US5624869A

公开(公告)日：1997-04-29

申请号：US226923

申请日：1994-04-13

Applicant: Paul D. Agnello ,  Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Matthew W. Copel ,  Francois M. d'Heurle ,  Qi-Zhong Hong

Inventor： Paul D. Agnello ,  Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Matthew W. Copel ,  Francois M. d'Heurle ,  Qi-Zhong Hong

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28518 ,  Y10S438/934

Abstract: A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.

Abstract translation: 涉及其的方法和装置，用于稳定二硅化硅/单晶硅，非晶硅，多晶硅，锗化锗/结晶锗，多晶锗结构或其他半导体材料结构，使得高温处理步骤（高于750° C.）不会降低二硅化钴/硅结构的结构质量。 该方法的步骤包括通过使钴与基底材料反应和/或二硅化物或锗化物在基底上共沉积形成二硅化物或锗化物，向铂中添加铂或氮的选择性元素 并通过标准退火处理形成二硅化物或锗化物。 另外也可以分别在二硅化物或锗化物形成之后形成二硅化钴或锗化钴。 结果，二硅化物或锗化锗在结构上降解的退火温度的上限增加。