公开(公告)号：US07018856B2

公开(公告)日：2006-03-28

申请号：US10768882

申请日：2004-01-29

Applicant: Chia-Ching Wan ,  Min-Ta Yu

Inventor： Chia-Ching Wan ,  Min-Ta Yu

IPC: H01L21/66 ,  H01L21/20 ,  H01L21/36 ,  H01L21/44 ,  G01R31/26

CPC classification number: H01L22/34 ,  Y10S438/934

Abstract: A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each dopant or impurity to be quantified. On each calibration standard wafer in the set is provided a silicon matrix incorporated with one of various concentrations, by weight, of the dopant or impurity in the silicon. The atomic concentration of the dopant or impurity in the silicon on each wafer in the set is measured. A calibration curve is then prepared in which the silicon/dopant or silicon/impurity ratio on each calibration standard wafer in the set is plotted versus the atomic concentration of the dopant or impurity in the silicon on the wafer.

Abstract translation: 多点校准标准和制造校准标准的方法，其用于量化硅基质中掺杂剂或杂质的剂量或浓度。 校准标准包括用于要量化的每种掺杂剂或杂质的一组校准标准晶片。 在组中的每个校准标准晶片上提供了一个硅基质，其掺入了硅中掺杂剂或杂质重量的各种浓度之一。 测量组中每个晶片上的硅中的掺杂剂或杂质的原子浓度。 然后制备校准曲线，其中在该组中的每个校准标准晶片上的硅/掺杂剂或硅/杂质比相对于晶片上的硅中的掺杂剂或杂质的原子浓度作图。

公开(公告)号：US5728598A

公开(公告)日：1998-03-17

申请号：US685815

申请日：1996-07-24

Applicant: Hsiao-Chia Wu ,  Jung Kao ,  Thomas Chang

Inventor： Hsiao-Chia Wu ,  Jung Kao ,  Thomas Chang

IPC: H01L21/8244

CPC classification number: H01L27/11 ,  Y10S438/934

Abstract: The present invention relates to a method of fabricating a SRAM cell that has a low stand-by current. A second polysilicon layer which is used as polysilicon resistor is exactly over a first polysilicon layer. The double polysilicon layer is utilized to reduced a stand-by current. A electric field is generated between the two layers caused by applying different voltage to the two polysilicon layer respectively, and the carriers in the second polysilicon layer will be repeled to form a depletion region, which will increase the resistance of the second polysilicon layer. Therefore, the stand-by current (Isb) will be reduced.

Abstract translation: 本发明涉及一种具有低备用电流的SRAM单元的制造方法。 用作多晶硅电阻器的第二多晶硅层正好在第一多晶硅层之上。 利用双重多晶硅层来降低备用电流。 通过分别对两个多晶硅层施加不同的电压而在两层之间产生电场，并且第二多晶硅层中的载流子将被排斥以形成耗尽区，这将增加第二多晶硅层的电阻。 因此，待机电流（Isb）将会降低。

公开(公告)号：US5686359A

公开(公告)日：1997-11-11

申请号：US569025

申请日：1995-12-07

Applicant: Steven Glenn Meester ,  Arun Kumar Nanda ,  Cletus Walter Wilkins

Inventor： Steven Glenn Meester ,  Arun Kumar Nanda ,  Cletus Walter Wilkins

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  Y10S438/934

Abstract: The specification describes a process for siliciding silicon metallization with titanium. The process requires two anneal steps and is based on careful control of operating parameters during the first anneal step. A prescription is given relating time and temperature of anneal, and titanium film thickness, to silicide resistivity. Proper choice of parameters also minimizes variables in the process.

Abstract translation: 本说明书描述了用钛硅化硅金属化的方法。 该过程需要两个退火步骤，并且基于在第一退火步骤期间对操作参数的仔细控制。 给出了退火时间和温度以及钛膜厚度与硅化物电阻率的处方。 参数的正确选择也使过程中的变量最小化。

公开(公告)号：US5308789A

公开(公告)日：1994-05-03

申请号：US124790

申请日：1993-09-22

Applicant: Yasushi Yoshimura ,  Takeshi Akatsuka ,  Junichi Okada

Inventor： Yasushi Yoshimura ,  Takeshi Akatsuka ,  Junichi Okada

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/322 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/2252 ,  H01L21/3225 ,  Y10S148/126 ,  Y10S438/909 ,  Y10S438/92 ,  Y10S438/934

Abstract: In a method of preparing a diffused silicon device substrate for use in the fabrication of a MOS power device, a drive-in diffusion step is followed by a thermal donor formation heat treatment which is achieved by heating the silicon device substrate at a temperature from 400.degree. to 500.degree. C. for 1 to 20 hours and in a gas atmosphere containing oxygen gas, and subsequently a thermal donor formation retarding heat treatment is performed by heating the silicon device substrate at a temperature of from 600.degree. to 700.degree. C. for 8 to 24 hours in a gas atmosphere containing oxygen gas.

Abstract translation: 在制备用于制造MOS功率器件的扩散硅器件衬底的方法中，驱动扩散步骤之后是热施主形成热处理，其通过在400℃的温度下加热硅器件衬底而实现 在500℃〜100℃下，在含有氧气的气氛中，通过在600℃〜700℃的温度下加热硅器件基板，进行热供体形成延迟热处理， 在含有氧气的气体气氛中8至24小时。

公开(公告)号：US5173443A

公开(公告)日：1992-12-22

申请号：US544772

申请日：1990-06-27

Applicant: V. Warren Biricik ,  James M. Rowe ,  Paul Kraatz ,  John W. Tully ,  Wesley J. Thompson ,  Rudolph W. Modster

Inventor： V. Warren Biricik ,  James M. Rowe ,  Paul Kraatz ,  John W. Tully ,  Wesley J. Thompson ,  Rudolph W. Modster

IPC: G02B1/10

CPC classification number: G02B1/10 ,  Y10S148/056 ,  Y10S148/058 ,  Y10S148/08 ,  Y10S438/934

Abstract: Methods are disclosed for making semiconductor windows which are transparent to light in the infrared range which have good electrical conductivity and are formed of a substrate material (11) having a semiconductor coating (14) having a dopant included therein. The coating is diffused, grown or deposited on one surface of the substrate and is controlled to obtain both low electrical resistivity and high infrared transmissivity. The coating can be formed of the same material as the substrate or can be a different material. Windows having particular thermal properties are formed utilizing zinc selenide and zinc sulfide as the substrate.

Abstract translation: 公开了制造半导体窗的方法，所述半导体窗对于具有良好导电性的红外范围的光是透明的，并且由其中包含掺杂剂的半导体涂层（14）的基板材料（11）形成。 涂层扩散，生长或沉积在衬底的一个表面上，并被控制以获得低电阻率和高红外透射率。 涂层可以由与基底相同的材料形成，或者可以是不同的材料。 具有特殊热性能的窗口是利用硒化锌和硫化锌作为基底形成的。

公开(公告)号：US5110758A

公开(公告)日：1992-05-05

申请号：US709060

申请日：1991-06-03

Applicant: Ira E. Baskett

Inventor： Ira E. Baskett

IPC: H01C17/24 ,  H01L21/329

CPC classification number: H01L29/66166 ,  H01C17/2408 ,  Y10S148/071 ,  Y10S438/934

Abstract: An improved method of trimming resistors by metal migration by local heating (18,21) of the resistor (23) to allow a reduced level of electric current to be used. The resistor is then trimmed by application of short pulses of high current causing metal migration (22). Each pulse decreases the resistance progressively until a desired final value is achieved. The reduced level of current of the improved method requires a reduced voltage across the resistor thus extending the earlier method to allow higher valued resistors, or lower breakdown voltages. The localized heating (18,21) is also used to anneal the migrated metal after trimming to increase the long term stability of the resistor (23). The intensity of the localized heating (18,21) can be varied to induce a desired shape in the migrated metal (22).

Abstract translation: 通过电阻器（23）的局部加热（18,21）通过金属迁移来修整电阻器的改进方法，以允许使用降低的电流水平。 然后通过施加引起金属迁移的高电流的短脉冲来修整电阻器（22）。 每个脉冲逐渐减小电阻，直到达到所需的最终值。 改进方法的电流降低需要在电阻器两端降低电压，从而延长早期方法以允许较高值的电阻或更低的击穿电压。 局部加热（18,21）也用于在修剪后退火迁移的金属以增加电阻器（23）的长期稳定性。 可以改变局部加热（18,21）的强度以在迁移的金属（22）中诱导期望的形状。

公开(公告)号：US5051376A

公开(公告)日：1991-09-24

申请号：US463642

申请日：1990-01-11

Applicant: Yutaka Yamada ,  Toshihiko Ibuka ,  Fumio Orito ,  Yuichi Seta ,  Shin-ichiro Kawabata

Inventor： Yutaka Yamada ,  Toshihiko Ibuka ,  Fumio Orito ,  Yuichi Seta ,  Shin-ichiro Kawabata

IPC: H01L21/265 ,  H01L21/324

CPC classification number: H01L21/26546 ,  H01L21/3245 ,  Y10S438/934

Abstract: A method for producing a semiconductor device comprises the steps of: preparing a III.sub.b -V.sub.b group compound single crystalline semiconductor substrate produced by a liquid encapsulated Czochralski process, the single crystalline semiconductor substrate having a carbon concentration of 1.times.10.sup.15 cm.sup.-3 or less, implanting conductive impurity ions into the single crystalline semiconductor substrate and then annealing, and a semiconductor device produced by this method.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：制备通过液体封装的Czochralski工艺制备的IIIb -Vb族化合物单晶半导体衬底，该单晶半导体衬底的碳浓度为1×10 15 cm -3以下，注入导电 杂质离子进入单晶半导体衬底，然后退火，以及通过该方法制造的半导体器件。

公开(公告)号：US5023201A

公开(公告)日：1991-06-11

申请号：US575460

申请日：1990-08-30

Applicant: David Stanasolovich ,  Leslie H. Allen ,  James W. Mayer

Inventor： David Stanasolovich ,  Leslie H. Allen ,  James W. Mayer

IPC: H01L21/285 ,  H01L21/768

CPC classification number: H01L21/28562 ,  H01L21/76879 ,  Y10S438/934

Abstract: An improved process for preparing selective deposition of conductive metals on disilicide encroachment barriers allows the construction of integrated circuit components wherein the metal/disilicide interface is substantially free of O and/or F contamination. The level of interfacial oxygen and/or fluorine contamination in the selective W deposition on the TiSi.sub.2 was substantially reduced or eliminated by first forming a C49 TiSi.sub.2 phase on a substrate, selectively depositing W on the C49 TiSi.sub.2 phase and thereafter annealing at a (minimum) temperature sufficient to convert the high resistivity phase C49 TiSi.sub.2 to the low resistivity phase C54 TiSi.sub.2.

Abstract translation: 用于制备导电金属在二硅化物侵入屏障上的选择性沉积的改进方法允许构建集成电路部件，其中金属/二硅化物界面基本上不含O和/或F污染物。 通过首先在衬底上形成C49TiSi2相，在C49TiSi2相上选择性地沉积W，然后以（最小）的方式退火，基本上减少或消除了选择性W沉积在TiSi 2上的界面氧和/或氟污染物的水平， 温度足以将高电阻率相C49TiSi2转化为低电阻相C54 TiSi2。

公开(公告)号：US4579601A

公开(公告)日：1986-04-01

申请号：US635434

申请日：1984-07-27

Applicant: Shuichi Samata ,  Yoshiaki Matsushita

Inventor： Shuichi Samata ,  Yoshiaki Matsushita

IPC: H01L21/70 ,  H01L21/322 ,  H01L21/324 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/167 ,  H01L21/20 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L27/10844 ,  H01L21/322 ,  H01L21/324 ,  H01L29/167 ,  Y10S438/934 ,  Y10S438/953

Abstract: A method for manufacturing a semiconductor device has the steps of: forming a first thin single-crystal semiconductor layer on a semiconductor substrate of one conductivity type which contains oxygen, the first thin single-crystal semiconductor layer having a higher resistivity than that of the semiconductor substrate and having the same conductivity type as that of the semiconductor substrate; ion-implanting an electrically inactive impurity in the first thin single-crystal semiconductor layer; forming a second thin single-crystal semiconductor layer on the first thin single-crystal semiconductor layer, the second thin single-crystal semiconductor layer having the same conductivity type as that of the semiconductor substrate and having a higher resistivity than that of the semiconductor substrate; performing annealing for not less than four hours at a temperature of 550.degree. C. to 900.degree. C. after the electrically inactive impurity is ion-implanted; and forming a cell of a dynamic random access memory in the second thin single-crystal semiconductor layer, the cell having one transistor and one capacitor.

Abstract translation: 半导体器件的制造方法具有以下步骤：在含有氧的一种导电型的半导体衬底上形成第一薄型单晶半导体层，第一薄型单晶半导体层的电阻率高于半导体 并且具有与半导体衬底相同的导电类型; 在第一薄单晶半导体层中离子注入电惰性杂质; 在所述第一薄单晶半导体层上形成第二薄单晶半导体层，所述第二薄单晶半导体层具有与所述半导体衬底相同的导电类型并且具有比所述半导体衬底更高的电阻率; 在离子注入不活泼的杂质后，在550〜900℃的温度下进行不少于4小时的退火。 以及在所述第二薄单晶半导体层中形成动态随机存取存储器的单元，所述单元具有一个晶体管和一个电容器。

公开(公告)号：US4560583A

公开(公告)日：1985-12-24

申请号：US626189

申请日：1984-06-29

Applicant: Tor W. Moksvold

Inventor： Tor W. Moksvold

IPC: H01L27/04 ,  H01C17/23 ,  H01L21/02 ,  H01L21/822 ,  H01L27/08 ,  H01L21/66

CPC classification number: H01L28/20 ,  H01C17/23 ,  H01L27/0802 ,  Y10S438/934 ,  Y10T29/49004

Abstract: Disclosed is a method of forming a precision integrated resistor element on a semiconductor wafer whose resistance value accurately corresponds to its nominal design value. The method comprises forming a resistor body in combination with a test resistor structure by conventional ion implantation or diffusion of suitable dopant in selected regions of the wafer. Then, by measuring the resistance(s) and width(s) of the test structure the variation .DELTA..rho..sub.s in sheet resistance and variation .DELTA.W in width due to process and image tolerances, respectively, are determined. Next, using .DELTA..rho..sub.s and .DELTA.W the adjustment in length .DELTA.L necessary to match the resistance of the resistance element with the nominal design value is calculated. Finally, this information (.DELTA.L) is supplied to an E-beam generating system to expose an E-beam sensitive contact level layer formed on the resistor body to form metal contact openings for the resistor body at a separation which provides a resistor having a resistance value corresponding to the design value.

Abstract translation: 公开了一种在半导体晶片上形成精密集成电阻元件的方法，其电阻值精确地对应于其标称设计值。 该方法包括通过传统的离子注入形成与测试电阻器结构结合的电阻体，或者在晶片的选定区域中扩散合适的掺杂剂。 然后，通过测量测试结构的电阻和宽度（s），分别确定由于工艺和图像公差而导致的薄层电阻和宽度变化量ΔTA的变化量ΔTATA宽度。 接下来，使用DELTA rho和DELTA W来计算将电阻元件的电阻与标称设计值相匹配所需的长度DELTA L的调整。 最后，将该信息（DELTA L）提供给电子束发生系统以暴露形成在电阻体上的电子束敏感的接触电平层，以在分离处形成用于电阻体的金属接触开口，其提供具有 电阻值对应设计值。