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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
    半导体器件及其制造方法

    公开(公告)号：US20110140243A1

    公开(公告)日：2011-06-16

    申请号：US12967373

    申请日：2010-12-14

    Applicant: Tadashi MISUMI ,  Shinya IWASAKI ,  Takahide SUGIYAMA

    Inventor： Tadashi MISUMI ,  Shinya IWASAKI ,  Takahide SUGIYAMA

    IPC: H01L29/30 ,  H01L21/322

    CPC classification number: H01L21/02238 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/32 ,  H01L29/6609 ,  H01L29/861 ,  H01L29/868 ,  Y10S438/92

    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.

    Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底的第一主表面上的第一电极和形成在半导体衬底的第二主表面上的第二电极。 半导体衬底包括其中氧空位缺陷的密度大于空位簇缺陷的密度的第一区域和空位簇缺陷的密度大于氧空位缺陷的密度的第二区域。

    METHOD FOR NON-THERMALLY NITRIDED GATE FORMATION FOR HIGH VOLTAGE DEVICES
    4.
    发明申请
    METHOD FOR NON-THERMALLY NITRIDED GATE FORMATION FOR HIGH VOLTAGE DEVICES 有权
    用于高电压装置的非热硝化栅层形成方法

    公开(公告)号：US20040067619A1

    公开(公告)日：2004-04-08

    申请号：US10264729

    申请日：2002-10-04

    Inventor： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

    IPC: H01L021/8234

    CPC classification number: H01L21/823462 ,  Y10S438/92

    Abstract: A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.

    Abstract translation: 提供了用于高压晶体管器件的非热氮化栅极形成的方法。 非热氮化栅极形成可用于双厚度栅极电介质结构的形成。 非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。 栅极电介质层的氮化破坏了栅极电介质层的表面。 通过相对较低温度的再氧化工艺去除栅介电层的受损表面。 低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。

    Method of manufacturing semiconductor device having shallow junction
    8.
    发明授权
    Method of manufacturing semiconductor device having shallow junction 有权
    制造具有浅结的半导体器件的方法

    公开(公告)号：US06218270B1

    公开(公告)日：2001-04-17

    申请号：US09261223

    申请日：1999-03-03

    Applicant: Tomoko Yasunaga

    Inventor： Tomoko Yasunaga

    IPC: H01L21425

    CPC classification number: H01L21/324 ,  H01L21/2652 ,  H01L21/31662 ,  Y10S438/92

    Abstract: A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.

    Abstract translation: 公开了一种制造具有含有杂质扩散层的硅衬底的半导体器件的方法，其包括以3keV的加速电压通过厚度为2.5nm或更小的氧化硅膜将杂质掺杂到硅衬底的步骤 所述氧化硅膜形成在所述硅基板上，并且所述氧化物膜残留在所述硅基板上。

    MOS device structure and integration method
    9.
    发明授权
    MOS device structure and integration method 失效
    MOS器件结构和集成方法

    公开(公告)号：US5691212A

    公开(公告)日：1997-11-25

    申请号：US721665

    申请日：1996-09-27

    Applicant: Chaochieh Tsai ,  Shun-Liang Hsu

    Inventor： Chaochieh Tsai ,  Shun-Liang Hsu

    IPC: H01L21/336 ,  H01L21/768 ,  H01L21/265

    CPC classification number: H01L29/66575 ,  H01L21/76895 ,  H01L29/41783 ,  Y10S438/92 ,  Y10S438/966

    Abstract: This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600.degree. C. in nitrogen converts the deposited silicon layer into elevated source and drains. A refractory metal, such as titanium is then deposited over the substrate and, upon rapid thermal annealing, reacts with the elevated source and drain polysilicon to form silicide without consuming the substrate silicon, and without ill effect on the source/drain junctions in the single crystalline silicon. The chance of silicide bridging is greatly reduced due to the special geometry of the novel sidewall oxide spacers.

    Abstract translation: 本发明描述了一种用于形成用于MOSFET中的自对准硅化物的新方法，以及具有升高的源极和漏极的MOSFET器件的新结构，其目的是减少硅化物穿入到源极和漏极结中以消除结尖峰 在硅化物和硅衬底之间获得更平滑的界面，并且减少栅极和源极和漏极上的硅化物桥接的机会。 通过在栅极侧壁上已经用场氧化物，栅极氧化物，多晶硅栅极和氮化硅间隔物图案化的硅衬底上沉积硅非晶层来制造新结构。 然后通过首先将氮注入到非晶硅层的水平表面中并随后在不暴露于氮注入的垂直侧壁上热氧化非晶硅的一部分来创建新的氧化物侧壁间隔物。 随后在氮气中在600℃退火的掺杂剂注入将沉积的硅层转化为升高的源和排水。 然后将难熔金属（例如钛）沉积在衬底上，并且在快速热退火时，与升高的源极和漏极多晶硅反应形成硅化物，而不消耗衬底硅，并且对单个源极/漏极结没有不利影响 晶体硅。 由于新型侧壁氧化物间隔物的特殊几何形状，硅化物桥接的机会大大降低。

    Method for reducing lateral dopant diffusion
    10.
    发明授权
    Method for reducing lateral dopant diffusion 失效
    减少横向掺杂剂扩散的方法

    公开(公告)号：US5506169A

    公开(公告)日：1996-04-09

    申请号：US326268

    申请日：1994-10-20

    Applicant: Richard L. Guldi

    Inventor： Richard L. Guldi

    IPC: H01L21/22 ,  H01L21/302

    CPC classification number: H01L21/22 ,  Y10S438/92

    Abstract: A process is disclosed for inhibiting lateral diffusion of dopants in a semiconductive material. At least one conductivity dependent region is formed in the semiconductor, and a blocking layer is provided in overlying relation with the conductivity dependent region. Interstitial sites or vacancies are introduced into the conductivity dependent region in accordance with the diffusion mechanism of a selected dopant, and dopant is diffused into the semiconductor in a direction that is substantially transverse to the semiconductor upper surface while inhibiting with the introduced interstitial sites or vacanies lateral diffusion of the dopant into the conductivity dependent region.

    Abstract translation: 公开了一种抑制半导体材料中掺杂剂的横向扩散的方法。 在半导体中形成至少一个导电性相关区域，并且以与导电性依赖区域重叠的关系提供阻挡层。 根据所选择的掺杂剂的扩散机理，将间隙位置或空位引入到导电性相关区域中，并且掺杂剂在基本横向于半导体上表面的方向上扩散到半导体中，同时抑制所引入的间隙位置或空位 掺杂剂向导电性依赖区域的横向扩散。

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