公开(公告)号：US20030151141A1

公开(公告)日：2003-08-14

申请号：US10374965

申请日：2003-02-28

Applicant: Fujitsu Limited

Inventor： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC: H01L023/48

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: There is provided a structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

公开(公告)号：US20020076909A1

公开(公告)日：2002-06-20

申请号：US10013506

申请日：2001-12-13

Applicant: FUJITSU LIMITED

Inventor： Hirohisa Matsuki ,  Hiroyuki Matsui

IPC: F27D005/00 ,  F27D013/00 ,  H01L021/44

CPC classification number: B23K35/38 ,  B23K35/262 ,  B23K35/268 ,  B23K35/3618 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166

Abstract: There is provided a semiconductor device manufacturing method which comprising the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing a formic acid to heat the solder bumps. Accordingly, the solder bumps can be formed without the use of flux not to generate voids in the solder layer, and also the cleaning required after the solder bumps are formed can be omitted.

Abstract translation: 提供了一种半导体器件制造方法，其包括以下步骤：在半导体器件的下面的金属膜上形成焊料凸块，并将半导体器件和焊料层放置在含有甲酸的减压气氛中以加热焊料凸块。 因此，可以在不使用焊剂的情况下形成焊料凸块而不在焊料层中产生空隙，并且可以省略在形成焊料凸块之后所需的清洁。

公开(公告)号：US20040012088A1

公开(公告)日：2004-01-22

申请号：US10618721

申请日：2003-07-15

Applicant: FUJITSU LIMITED,

Inventor： Norio Fukasawa ,  Hirohisa Matsuki ,  Kenichi Nagashige ,  Yuzo Hamanaka ,  Muneharu Morioka

IPC: H01L023/48

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L24/29 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10S438/92 ,  Y10S438/978 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Abstract translation: 半导体器件在半导体芯片的主表面上具有树脂封装层，其上形成有多个凸起电极，其中半导体器件具有倒角表面或顶部边缘部分上的台阶表面，使得外部冲击或 施加到这种边缘部分的应力由台阶表面的倒角表面消散。

公开(公告)号：US20020030258A1

公开(公告)日：2002-03-14

申请号：US09766656

申请日：2001-01-23

Applicant: FUJITSU LIMITED

Inventor： Norio Fukasawa ,  Toshimi Kawahara ,  Muneharu Morioka ,  Mitsunada Osawa ,  Yasuhiro Shinma ,  Hirohisa Matsuki ,  Masanori Onodera ,  Junichi Kasai ,  Shigeyuki Maruyama ,  Masao Sakuma ,  Yoshimi Suzuki ,  Masashi Takenaka

IPC: H01L023/02

CPC classification number: H01L21/568 ,  B29C43/18 ,  B29C2043/3444 ,  B29C2043/3628 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/566 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/0556 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1005 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.

Abstract translation: 一种方法包括：树脂密封步骤，在模具20的空腔28中，将布置有凸块12的半导体元件11的基板16设置在树脂密封步骤中，将树脂35供应到凸块12的位置，使得 形成密封凸块12的树脂层13，使由树脂层13密封的凸块12的至少端部露出使突出部12的端部从树脂层13露出的突出电极曝光工序，以及分离工序 与树脂层13一起切割基板16，使得半导体元件11彼此分离。

公开(公告)号：US20020121709A1

公开(公告)日：2002-09-05

申请号：US09895330

申请日：2001-07-02

Applicant: Fujitsu Limited

Inventor： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: There is provided a structure in which a phosphorusnullnickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorusnullnickel layer, a nickelnulltin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract translation: 提供了一种结构，其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍 - 锡合金层，富锡锡合金层和锡合金 焊料层依次形成在电极上。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US20020014661A1

公开(公告)日：2002-02-07

申请号：US09735476

申请日：2000-12-14

Applicant: FUJITSU LIMITED

Inventor： Tadahiro Okamoto ,  Hirohisa Matsuki

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.

Abstract translation: 制备从形成在晶片前表面上的具有多个半导体集成电路的半导体晶片分开的多个芯片，芯片的前表面被接合到第一晶片。 结合到第一晶片片的每个芯片的背面和侧表面被增强薄膜覆盖。 将多个芯片中的每一个从第一晶片片上移除。 可以抑制芯片的弯曲强度由于切屑和芯片裂纹而降低。

公开(公告)号：US20030164544A1

公开(公告)日：2003-09-04

申请号：US10214306

申请日：2002-08-08

Applicant: FUJITSU LIMITED

Inventor： Mitsutaka Sato ,  Tetsuya Fujisawa ,  Shigeyuki Maruyama ,  Junichi Kasai ,  Toshimi Kawahara ,  Toshio Hamano ,  Yoshihiro Kubota ,  Mitsunada Osawa ,  Yoshiyuki Yoneda ,  Kazuto Tsuji ,  Hirohisa Matsuki

IPC: H01L023/34

CPC classification number: H01L25/105 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2924/09701 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/82 ,  H05K7/1431 ,  H01L2924/00

Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.

公开(公告)号：US20030162320A1

公开(公告)日：2003-08-28

申请号：US10207815

申请日：2002-07-31

Applicant: FUJITSU LIMITED

Inventor： Masamitsu Ikumo ,  Hirohisa Matsuki

IPC: H01L021/48

CPC classification number: H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00

Abstract: A group of wires that bonds the first semiconductor chip and the second semiconductor chip together and extends on the first semiconductor chip is formed of a single plated film through plating in one continuous process. The second semiconductor chip is then bonded onto the first semiconductor chip to complete a semiconductor package.

Abstract translation: 将第一半导体芯片和第二半导体芯片结合在一起并在第一半导体芯片上延伸的一组电线通过一个连续工艺中的电镀由单个镀膜形成。 然后将第二半导体芯片接合到第一半导体芯片上以完成半导体封装。

公开(公告)号：US20020089054A1

公开(公告)日：2002-07-11

申请号：US10097817

申请日：2002-03-15

Applicant: FUJITSU LIMITED

Inventor： Norio Fukasawa ,  Hirohisa Matsuki ,  Kenichi Nagashige ,  Yuzo Hamanaka ,  Muneharu Morioka

IPC: H01L023/48

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L24/29 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10S438/92 ,  Y10S438/978 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Abstract translation: 半导体器件在半导体芯片的主表面上具有树脂封装层，其上形成有多个凸起电极，其中半导体器件具有倒角表面或顶部边缘部分上的台阶表面，使得外部冲击或 施加到这种边缘部分的应力由台阶表面的倒角表面消散。

公开(公告)号：US20020076908A1

公开(公告)日：2002-06-20

申请号：US09867545

申请日：2001-05-31

Applicant: FUJITSU LIMITED

Inventor： Yutaka Makino ,  Eiji Watanabe ,  Hirohisa Matsuki ,  Tetsuya Fujisawa

IPC: H01L021/44

CPC classification number: H01L21/288 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises the steps of: forming a wiring electrically connected to an electrode pad formed on a substrate, the wiring extending on the substrate; forming a post terminal by electroless plating so that the post terminal is electrically connected to the wiring; and providing a sealing resin so as to cover the substrate except a position at which the post terminal is formed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤：形成电连接到形成在基板上的电极焊盘的布线，所述布线在基板上延伸; 通过无电镀形成后端子，使得端子端子与布线电连接; 以及提供密封树脂以覆盖基板，除了形成端子的位置之外。