公开(公告)号：US06218270B1

公开(公告)日：2001-04-17

申请号：US09261223

申请日：1999-03-03

Applicant: Tomoko Yasunaga

Inventor： Tomoko Yasunaga

IPC: H01L21425

CPC classification number: H01L21/324 ,  H01L21/2652 ,  H01L21/31662 ,  Y10S438/92

Abstract: A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.

Abstract translation: 公开了一种制造具有含有杂质扩散层的硅衬底的半导体器件的方法，其包括以3keV的加速电压通过厚度为2.5nm或更小的氧化硅膜将杂质掺杂到硅衬底的步骤 所述氧化硅膜形成在所述硅基板上，并且所述氧化物膜残留在所述硅基板上。

公开(公告)号：US06190976B1

公开(公告)日：2001-02-20

申请号：US09198763

申请日：1998-11-24

Applicant: Seiichi Shishiguchi ,  Tomoko Yasunaga

Inventor： Seiichi Shishiguchi ,  Tomoko Yasunaga

IPC: H01L21336

CPC classification number: H01L29/665 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4941

Abstract: A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching. If unwanted grains of poly-Si or amorphous Si are grown on the first and second dielectric sidewalls in the selective epitaxial growth process, the unwanted grains are oxidized and removed, thereby preventing electrical short-circuit from occurring between the gate electrode and the first and second source/drain regions through the unwanted grains deposited on the first and second dielectric sidewalls.

Abstract translation: 提供了具有IGFET的半导体器件的制造方法，这使得可以通过沉积在其电介质侧壁上的导电晶粒来减小由IGFET的栅极电极和源极/漏极区域之间的电短路引起的电流泄漏。 在形成IGFET的基本结构之后，通过选择性外延生长工艺在第一和第二源/漏区上分别形成第一和第二单晶Si外延层。 然后，第一和第二单晶Si外延层的表面积被氧化，并且通过蚀刻去除第一和第二单晶Si外延层的氧化表面积。 如果在选择性外延生长工艺中在多晶硅或非晶Si的不想要的晶粒生长在第一和第二电介质侧壁上，则不需要的晶粒被氧化和去除，从而防止在栅电极和第一和第二电介质侧壁之间发生电短路 通过沉积在第一和第二电介质侧壁上的不需要的晶粒的第二源/漏区。

公开(公告)号：US06017823A

公开(公告)日：2000-01-25

申请号：US998626

申请日：1997-12-29

Applicant: Seiichi Shishiguchi ,  Tomoko Yasunaga ,  Akira Mineji

Inventor： Seiichi Shishiguchi ,  Tomoko Yasunaga ,  Akira Mineji

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L29/66628 ,  H01L21/2652 ,  H01L21/28052 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/665

Abstract: The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.

Abstract translation: 本发明提供一种在硅衬底表面上的栅极绝缘膜上的栅电极的侧壁上形成栅极侧壁绝缘膜的方法。 该方法包括以下步骤。 门侧壁绝缘膜选择性地形成在栅电极的侧壁上。 在栅电极的顶部和硅衬底表面上的至少任何一个上选择性地生长硅膜。 蚀刻栅极侧壁绝缘膜的表面区域。