Invention Grant
- Patent Title: Method of manufacturing semiconductor device having shallow junction
- Patent Title (中): 制造具有浅结的半导体器件的方法
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Application No.: US09261223Application Date: 1999-03-03
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Publication No.: US06218270B1Publication Date: 2001-04-17
- Inventor: Tomoko Yasunaga
- Applicant: Tomoko Yasunaga
- Priority: JP10-052219 19980304
- Main IPC: H01L21425
- IPC: H01L21425

Abstract:
A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.
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