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    INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
    3.
    发明申请
    INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION 审中-公开
    具有威盛特征的绝缘结构和用于BEOL整合的电介质衬里

    公开(公告)号：US20120199976A1

    公开(公告)日：2012-08-09

    申请号：US13448780

    申请日：2012-04-17

    Applicant: Chih-Chao Yang ,  Chao-Kun Hu

    Inventor： Chih-Chao Yang ,  Chao-Kun Hu

    IPC: H01L23/532

    CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49204

    Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

    Abstract translation: 一种互连结构，包括具有嵌入其中的第一导电材料的第一介电层的下部互连电平; 位于所述第一电介质层上的电介质覆盖层和所述第一导电材料的一些部分; 上部互连级别，包括具有填充有第二导电材料的至少一个通孔开口的第二介电层和填充有设置在其中的第二导电材料的至少一个覆盖的线路开口，其中所述至少一个通孔与第一导电材料接触 导电材料在下互连级别通过通孔气刨特征; 在所述至少一个通孔开口的侧壁上的电介质衬垫; 以及在所述至少一个通孔开口和所述至少一个覆盖线开口的侧壁和底部上的第一扩散阻挡层。 还提供了形成互连结构的方法。

    EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS
    4.
    发明申请
    EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS 有权
    电气保险丝应用的有效互连结构

    公开(公告)号：US20090278229A1

    公开(公告)日：2009-11-12

    申请号：US12119125

    申请日：2008-05-12

    Applicant: Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

    Inventor： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

    IPC: H01L23/525 ,  H01L21/768

    CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

    Abstract translation: 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流被提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

    On-chip Cu interconnection using 1 to 5 nm thick metal cap
    5.
    发明申请
    On-chip Cu interconnection using 1 to 5 nm thick metal cap 有权
    使用1至5nm厚的金属帽的片上Cu互连

    公开(公告)号：US20060160350A1

    公开(公告)日：2006-07-20

    申请号：US11037970

    申请日：2005-01-18

    Applicant: John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

    Inventor： John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

    IPC: H01L21/4763

    CPC classification number: H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

    Abstract translation: 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

    Reduced electromigration and stressed induced migration of copper wires by surface coating
    7.
    发明申请
    Reduced electromigration and stressed induced migration of copper wires by surface coating 有权
    通过表面涂层减少电迁移和应力诱导的铜线迁移

    公开(公告)号：US20050266673A1

    公开(公告)日：2005-12-01

    申请号：US11183773

    申请日：2005-07-19

    Applicant: Chao-Kun Hu ,  Robert Rosenberg ,  Judith Rubino ,  Carlos Sambucetti ,  Anthony Stamper

    Inventor： Chao-Kun Hu ,  Robert Rosenberg ,  Judith Rubino ,  Carlos Sambucetti ,  Anthony Stamper

    IPC: C23C18/16 ,  H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

    CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76864 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

    Abstract translation: 本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。 该涂层足够薄，以便消除对通过抛光的附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已被发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热 压力消除。 此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。 自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。 提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。 尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

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