公开(公告)号：US06835630B2

公开(公告)日：2004-12-28

申请号：US10376230

申请日：2003-03-03

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L218234

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底具有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US06821853B1

公开(公告)日：2004-11-23

申请号：US10159413

申请日：2002-05-31

Applicant: James F. Buller ,  Scott Luning

Inventor： James F. Buller ,  Scott Luning

IPC: H01L218234

CPC classification number: H01L21/823468 ,  H01L21/823462

Abstract: Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

Abstract translation: 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。

公开(公告)号：US06808976B1

公开(公告)日：2004-10-26

申请号：US09652714

申请日：2000-08-31

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L218234

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  Y10S438/957 ,  Y10S438/958

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

公开(公告)号：US06806136B1

公开(公告)日：2004-10-19

申请号：US10780416

申请日：2004-02-17

Applicant: Hsiu-Wen Hsu

Inventor： Hsiu-Wen Hsu

IPC: H01L218234

CPC classification number: H01L27/0682 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/94

Abstract: The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.

Abstract translation: 本发明一般涉及半导体制造，更具体地涉及同时形成电容器，电阻器和金属氧化物半导体。

公开(公告)号：US06803283B1

公开(公告)日：2004-10-12

申请号：US10261345

申请日：2002-09-30

Applicant: Jiun-Nan Chen

Inventor： Jiun-Nan Chen

IPC: H01L218234

CPC classification number: H01L27/112 ,  H01L27/11266

Abstract: A new method to form ROM devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. MOS gates are formed overlying the substrate. Ions are implanted into the substrate to form lightly doped drains for the MOS gates. A masking layer is used to offset the lightly doped drains from selective MOS gates to thereby form constant-OFF MOS gates. Spacers are next formed on the sidewalls of the MOS gates. Finally, ions are implanted into the substrate to form source and drain regions for the MOS gates to thereby complete the ROM devices in the manufacture of said integrated circuit device. The method may be extended to form ROM devices from Flash gates in a FlashROM process.

Abstract translation: 实现了在制造集成电路器件中形成ROM器件的新方法。 该方法包括提供半导体衬底。 形成覆盖衬底的MOS栅极。 将离子注入到衬底中以形成用于MOS栅极的轻掺杂漏极。 掩模层用于从选择性MOS栅极偏移轻掺杂的漏极，从而形成恒定的关闭MOS栅极。 接下来，在MOS门的侧壁上形成隔板。 最后，将离子注入到衬底中以形成用于MOS栅极的源区和漏区，从而在所述集成电路器件的制造中完成ROM器件。 该方法可以扩展为在FlashROM过程中从闪存门形成ROM器件。

公开(公告)号：US06794252B2

公开(公告)日：2004-09-21

申请号：US10254396

申请日：2002-09-25

Applicant: Antonio L. P. Rotondaro ,  Mark R. Visokay

Inventor： Antonio L. P. Rotondaro ,  Mark R. Visokay

IPC: H01L218234

CPC classification number: H01L21/28194 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/518

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Abstract translation: 提供了一种用于形成双功函数栅电极的方法。 介电层设置在基板的外侧。 在电介质层的外侧形成金属层。 在金属层的外部形成硅锗层。 去除硅 - 锗层的第一部分以暴露金属层的第一部分，硅 - 锗层的第二部分保留在金属层的第二部分上。 硅 - 锗金属化合物层由硅 - 锗层的第二部分和金属层的第二部分形成。 形成包括金属层的第一部分的第一栅电极。 形成包含硅 - 锗金属化合物层的第二栅电极。

公开(公告)号：US06784059B1

公开(公告)日：2004-08-31

申请号：US09652044

申请日：2000-08-31

Applicant: Toshimitsu Taniguchi ,  Takashi Arai ,  Masashige Aoyama ,  Kazuhiro Yoshitake

Inventor： Toshimitsu Taniguchi ,  Takashi Arai ,  Masashige Aoyama ,  Kazuhiro Yoshitake

IPC: H01L218234

CPC classification number: H01L29/7835 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1033 ,  H01L29/7833

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract translation: 本发明的特征在于，经由栅极氧化膜9形成在P型阱3上的栅极27F，高浓度N型源极层和高浓度N型漏极层15 分别形成为分别围绕N型源极层和N型漏极层10的栅极电极和低浓度N型源极层以及低浓度H型漏极层，分别由P 设置形成在栅电极27F下方的主体层。

公开(公告)号：US06767778B2

公开(公告)日：2004-07-27

申请号：US10230809

申请日：2002-08-29

Applicant: Zhongze Wang ,  Inna V. Patrick

Inventor： Zhongze Wang ,  Inna V. Patrick

IPC: H01L218234

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.

Abstract translation: 公开了一种用于通过附加的低剂量超深源极/漏极注入来减少结电容的半导体器件及其制造方法。 特别地，在间隔物形成之后进行超深度注入，以显着降低沟道区中的结电容。

公开(公告)号：US06762100B2

公开(公告)日：2004-07-13

申请号：US10364399

申请日：2003-02-12

Applicant: Jin Soo Kim

Inventor： Jin Soo Kim

IPC: H01L218234

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on the semiconductor substrate, and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.

Abstract translation: 掩模ROM单元及其制造方法公开在半导体基板中，在一个方向上形成有第一导电类型的半导体基板和第二导电类型的多个杂质扩散区域，其间具有预定距离， 对应于每个杂质扩散区域形成在半导体衬底的一部分上的绝缘层，形成在半导体衬底上的栅极绝缘层和以预定间隔形成在栅极绝缘层和绝缘层上的多个导电线， 垂直于杂质扩散区。

公开(公告)号：US06743679B2

公开(公告)日：2004-06-01

申请号：US10126438

申请日：2002-04-19

Applicant: Xi-Wei Lin ,  Gwo-Chung Tai

Inventor： Xi-Wei Lin ,  Gwo-Chung Tai

IPC: H01L218234

CPC classification number: H01L21/82345

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract translation: 本发明包括一种制造双电压集成电路器件的技术。 在半导体衬底上形成栅介质层，并在电介质层上形成栅极材料层。 栅极材料层的第一区域被掺杂到第一非零电平，并且栅极材料电平的第二区域被掺杂到大于第一电平的第二非零电平。 第一场效应晶体管被定义为具有由第一区域形成的第一栅极。 此外，限定了第二场效应晶体管，其具有由第二区域形成的第二栅极。 根据第一电平和第二电平之间的差，第一晶体管可在大于第二晶体管的栅极阈值电压下操作。