公开(公告)号：US07741694B2

公开(公告)日：2010-06-22

申请号：US10950611

申请日：2004-09-27

Applicant: Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

Inventor： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC: H01L29/00

CPC classification number: H01L21/8224 ,  H01L27/0821 ,  H01L29/7322

Abstract: A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract translation: 根据本发明的半导体集成电路器件包括用作小信号部分的第一和第二岛区中的衬底和外延层之间的N型嵌入扩散区域。 N型嵌入扩散区域连接到具有电源电位的N型扩散区域。 因此，衬底和外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入式扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US07439578B2

公开(公告)日：2008-10-21

申请号：US11617517

申请日：2006-12-28

Applicant: Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

Inventor： Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06

CPC classification number: H01L29/7809 ,  H01L21/743 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/781

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Abstract translation: 半导体器件包括形成在半导体衬底的表面中的沟槽。 导体嵌入在沟槽中。 导电层被布置成与半导体衬底的表面上的沟槽相邻。 包括由导体和导电层之一提供的源和由导体和导电层中的另一个提供的漏极的半导体元件形成在半导体元件形成区中。 在整个半导体元件形成区域的半导体衬底内嵌有平面布线层，并与导体连接。

公开(公告)号：US20050077571A1

公开(公告)日：2005-04-14

申请号：US10950610

申请日：2004-09-27

Applicant: Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

Inventor： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC: H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L31/113

CPC classification number: H01L27/0826 ,  H01L21/8224 ,  H01L27/0821

Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract translation: 根据本发明的半导体集成电路器件包括在用作小信号部分的岛区中的衬底和第一外延层之间的N型嵌入扩散区域。 因此，衬底和第一外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US07964915B2

公开(公告)日：2011-06-21

申请号：US11708682

申请日：2007-02-21

Applicant: Shuji Tanaka ,  Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Kazuhiro Yoshitake

Inventor： Shuji Tanaka ,  Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Kazuhiro Yoshitake

IPC: H01L29/76 ,  H01L31/113

CPC classification number: H01L29/0878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/404 ,  H01L29/66659 ,  H01L29/7835

Abstract: The invention provides a high voltage MOS transistor having a high source/drain breakdown voltage of about 300V and a low on-resistance. An N-type body layer is formed extending from a source layer side to under a gate electrode. A P-type second drift layer is formed in an epitaxial semiconductor layer by being diffused deeper than a first drift layer, extending from under the first drift layer to under the gate electrode and forming a PN junction with the body layer under the gate electrode. A surface of the body layer between this second drift layer and the source layer serves as a channel region. The first drift layer is formed at a distance from a left end of the gate electrode where electric field concentration easily occurs.

Abstract translation: 本发明提供了具有约300V的高源/漏击穿电压和低导通电阻的高压MOS晶体管。 形成从源极侧向栅电极延伸的N型体层。 通过比第一漂移层更深地扩散在外延半导体层中形成P型第二漂移层，该第一漂移层从第一漂移层下方延伸到栅电极下方，并与栅电极下方的体层形成PN结。 该第二漂移层和源极层之间的体层的表面用作沟道区。 第一漂移层形成在距离电极容易发生电场浓度的栅电极的左端一定距离处。

公开(公告)号：US20050087771A1

公开(公告)日：2005-04-28

申请号：US10949569

申请日：2004-09-24

Applicant: Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

Inventor： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732 ,  H01L29/745

CPC classification number: H01L27/0821 ,  H01L27/0647

Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

Abstract translation: 根据本发明的半导体集成电路器件包括在第二岛区中的二极管。 二极管的阳极区域和具有水平PNP晶体管的第一岛区域中的分割区域彼此电连接; 二极管的阴极区域和功率NPN晶体管的集电极区域彼此电连接。 因此，具有水平PNP晶体管的第一岛状区域中的分割区域的电位低于其他岛状区域中的分割区域，从而可以防止自由载流子（电子）向水平PNP晶体管的流入。

公开(公告)号：US07381998B2

公开(公告)日：2008-06-03

申请号：US10949569

申请日：2004-09-24

Applicant: Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

Inventor： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC: H01L29/861

CPC classification number: H01L27/0821 ,  H01L27/0647

Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

Abstract translation: 根据本发明的半导体集成电路器件包括在第二岛区中的二极管。 二极管的阳极区域和具有水平PNP晶体管的第一岛区域中的分割区域彼此电连接; 二极管的阴极区域和功率NPN晶体管的集电极区域彼此电连接。 因此，具有水平PNP晶体管的第一岛状区域中的分割区域的电位低于其他岛状区域中的分割区域，从而可以防止自由载流子（电子）向水平PNP晶体管的流入。

公开(公告)号：US20070166925A1

公开(公告)日：2007-07-19

申请号：US11617517

申请日：2006-12-28

Applicant: Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

Inventor： Yasuhiro Takeda ,  Mitsuaki Morigami ,  Satoru Shimada ,  Kazuhiro Yoshitake ,  Shuichi Kikuchi ,  Seiji Otake ,  Toshiyuki Ohkoda

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/7809 ,  H01L21/743 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/781

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Abstract translation: 半导体器件包括在半导体衬底的表面中形成的沟槽。 导体嵌入在沟槽中。 导电层被布置成与半导体衬底的表面上的沟槽相邻。 包括由导体和导电层之一提供的源和由导体和导电层中的另一个提供的漏极的半导体元件形成在半导体元件形成区域中。 在整个半导体元件形成区域的半导体衬底内嵌有平面布线层，并与导体连接。

公开(公告)号：US06784059B1

公开(公告)日：2004-08-31

申请号：US09652044

申请日：2000-08-31

Applicant: Toshimitsu Taniguchi ,  Takashi Arai ,  Masashige Aoyama ,  Kazuhiro Yoshitake

Inventor： Toshimitsu Taniguchi ,  Takashi Arai ,  Masashige Aoyama ,  Kazuhiro Yoshitake

IPC: H01L218234

CPC classification number: H01L29/7835 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1033 ,  H01L29/7833

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract translation: 本发明的特征在于，经由栅极氧化膜9形成在P型阱3上的栅极27F，高浓度N型源极层和高浓度N型漏极层15 分别形成为分别围绕N型源极层和N型漏极层10的栅极电极和低浓度N型源极层以及低浓度H型漏极层，分别由P 设置形成在栅电极27F下方的主体层。

公开(公告)号：US07067899B2

公开(公告)日：2006-06-27

申请号：US10950610

申请日：2004-09-27

Applicant: Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

Inventor： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC: H01L29/00

CPC classification number: H01L27/0826 ,  H01L21/8224 ,  H01L27/0821

Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract translation: 根据本发明的半导体集成电路器件包括在用作小信号部分的岛区中的衬底和第一外延层之间的N型嵌入扩散区域。 因此，衬底和第一外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US5940708A

公开(公告)日：1999-08-17

申请号：US690485

申请日：1996-07-31

Applicant: Masashige Aoyama ,  Kazuhiro Yoshitake

Inventor： Masashige Aoyama ,  Kazuhiro Yoshitake

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66659 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/7835

Abstract: A method for the production of a semiconductor integrated circuit device is disclosed, wherein the formation of lateral wall spacers for high voltage MOS transistor is implemented by forming a resist film for covering at least an insulating film formed on a drain region of low impurity concentration in the proximity of a gate electrode, masking the resist film, and etching the parts of the insulating film destined to give rise to the lateral wall spacers.

Abstract translation: 公开了一种制造半导体集成电路器件的方法，其中通过形成用于覆盖形成在低杂质浓度的漏区上的至少绝缘膜的抗蚀剂膜来实现用于高压MOS晶体管的侧壁间隔物的形成 栅电极的接近，掩模抗蚀剂膜，以及蚀刻绝缘膜的部分，以产生侧壁间隔物。