公开(公告)号：US20100290265A1

公开(公告)日：2010-11-18

申请号：US12847531

申请日：2010-07-30

Applicant: Vishnu K. Agarwal ,  Howard E. Rhodes

Inventor： Vishnu K. Agarwal ,  Howard E. Rhodes

IPC: G11C11/22 ,  H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 装置和系统可以包括在表面上包括两个或多个不相似和邻接的金属层的电极结构，一些由间隙隔开的电极结构; 以及覆盖并直接邻接一些电极结构的基于聚合物的铁电层。 方法可以包括形成和操作装置和系统的动作。 公开了附加装置，系统和方法。

公开(公告)号：US07446363B2

公开(公告)日：2008-11-04

申请号：US11361111

申请日：2006-02-24

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L27/108 ,  H01L29/92

CPC classification number: H01L21/02183 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/02356 ,  H01L27/1085 ,  H01L28/55

Abstract: The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer. A second capacitor electrode layer is formed over the substantially amorphous second high K capacitor dielectric material layer.

Abstract translation: 本发明包括集成电路和形成电容器的方法。 在一个实施方式中，集成电路包括具有第一电容器电极，第二电容器电极和接收在其间的高K电容器电介质区域的电容器。 高K电容电介质区域具有高K基本无定形材料层和高K基本结晶材料层。 在一个实施方式中，电容器形成方法包括在衬底上形成第一电容器电极层。 在第一电容器电极层上沉积基本无定形的第一高K电容介电材料层。 基本无定形的高K第一电容器介电材料层被转换成基本上是结晶的。 在转换之后，在基本上晶体的第一高K电容介电材料层上沉积基本非晶的第二高K电容器介电材料层。 第二电容器电极层形成在基本无定形的第二高K电容电介质材料层上。

公开(公告)号：US07390712B2

公开(公告)日：2008-06-24

申请号：US11796773

申请日：2007-04-30

Applicant: Cem Basceri ,  Vishnu K. Agarwal ,  Dan Gealy

Inventor： Cem Basceri ,  Vishnu K. Agarwal ,  Dan Gealy

IPC: H01L21/8242 ,  H01L21/441

CPC classification number: H01L21/02183 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/65 ,  H01L28/91

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Abstract translation: 描述了在高温下抑制电介质降解的系统，装置，结构和方法。 讨论了增强型电容器。 增强电容器包括第一电极，包括五氧化二钽的电介质和具有化合物的第二电极。 该化合物包括第一物质和第二物质。 第二电极包括痕量的第一物质。 当电介质结晶期间第一物质的痕量被氧化时，半导体结构的形态保持稳定。 在一个实施例中，电介质的晶体结构基本上描述了（001）晶格平面。

公开(公告)号：US07238616B2

公开(公告)日：2007-07-03

申请号：US11090204

申请日：2005-03-28

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L21/44

CPC classification number: H01L21/02274 ,  C23C16/452 ,  C23C16/482 ,  H01J37/32339 ,  H01J37/32357 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28556 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/314 ,  H01L21/67069 ,  H01L21/76864

Abstract: The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo-energy for maintaining activation of the active species or providing photo-energy for a non-plasma species during transfer through the transparent tube to the processing chamber. The source of photo-energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist processes by providing additional in-situ energy through a transparent window of the processing chamber. The system can be utilized for processes such as layer-by-layer annealing and deposition and also removal of contaminants from deposited layers.

Abstract translation: 本发明提供了一种处理系统，其包括用于形成活性气体种类的远程等离子体激活区域，耦合在远程激活区域和半导体处理室之间的透明传输管，以及用于维持活性物质活化的光能源 或者在通过透明管转移到处理室期间为非等离子体物质提供光能。 光能源最好包括一组UV灯。 还可以使用附加的UV灯来进一步维持活性种类并通过在处理室的透明窗口提供额外的原位能来辅助工艺。 该系统可用于逐层退火和沉积以及从沉积层去除污染物的工艺。

公开(公告)号：US07157324B2

公开(公告)日：2007-01-02

申请号：US10931513

申请日：2004-09-01

Applicant: Vishnu K. Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard E. Rhodes ,  Jeffrey A. McKee

Inventor： Vishnu K. Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard E. Rhodes ,  Jeffrey A. McKee

IPC: H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76232

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract translation: 在具有通过拉回工艺叠层的第一层和第二层而形成的掺杂注入区的衬底中，晶体管结构中不期望的晶体管泄漏变得大大降低。 衬底的一部分也具有沉积在其上的第一和第二层，限定了工艺叠层。 掺杂剂选择具有与底物相同的n-或p-型。 通过蚀刻，工艺堆叠的第一和第二层从衬底的沟槽壁拉回以形成植入区域。 由掺杂剂对植入区域的占用防止了不期望的晶体管泄漏，因为与第一层下方的衬底的中心区域相比，注入区域的电特性如此显着地改变，使植入区域的阈值电压升高到 约等于或大于中心区域中的基本均匀的阈值电压。

公开(公告)号：US07049191B1

公开(公告)日：2006-05-23

申请号：US09652993

申请日：2000-08-31

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L21/8234

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  Y10S438/957 ,  Y10S438/958

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

公开(公告)号：US07002202B2

公开(公告)日：2006-02-21

申请号：US10688823

申请日：2003-10-17

Applicant: Sam Yang ,  Vishnu K. Agarwal

Inventor： Sam Yang ,  Vishnu K. Agarwal

IPC: H01L27/108

CPC classification number: H01L28/56 ,  H01L27/10852 ,  H01L28/75

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US06974718B2

公开(公告)日：2005-12-13

申请号：US10762299

申请日：2004-01-23

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H04N3/15 ,  H04N9/04 ,  H01L21/00

CPC classification number: H04N9/045 ,  H04N5/37452

Abstract: CMOS image sensors have charge storage capacitors connected to various light sensitive and/or electrical elements. The capacity of the capacitors used for each pixel is tailored to the color to be detected. Charge storage capacitors may be formed entirely over a filed oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract translation: CMOS图像传感器具有连接到各种光敏元件和/或电元件的电荷存储电容器。 用于每个像素的电容器的容量被调整为要检测的颜色。 电荷存储电容器可以完全在CMOS成像器的电荷氧化物区域上形成，完全在像素传感器单元的有效区域上，或部分地在场氧化物区域上，部分地在像素传感器单元的有源像素区域上形成。

公开(公告)号：US06911381B2

公开(公告)日：2005-06-28

申请号：US10679822

申请日：2003-10-06

Applicant: Vishnu K. Agarwal ,  Gurtej S. Sandhu

Inventor： Vishnu K. Agarwal ,  Gurtej S. Sandhu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49 ,  H01L21/425

CPC classification number: H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

公开(公告)号：US06911371B2

公开(公告)日：2005-06-28

申请号：US09879335

申请日：2001-06-11

Applicant: Vishnu K. Agarwal ,  F. Daniel Gealy

Inventor： Vishnu K. Agarwal ,  F. Daniel Gealy

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/20

CPC classification number: H01L28/40 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5222 ,  H01L28/57 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer. Further, the barrier layer can be formed after forming the capacitor electrode or after forming the dielectric layer, for example, by using poor step coverage deposition methods.

Abstract translation: 电容器形成方法可以包括在衬底上形成绝缘层，并在衬底上形成阈值电压移动诱导材料的势垒层。 开口可以至少形成在绝缘层中，并且至少形成在开口内形成电容器电介质层。 阈值电压诱导材料可以设置在阻挡层之上，但是在运动中被延迟到由衬底包括的电子器件中。 电介质层可以包括氧化钽，并且阻挡层可以包括氮化硅。 提供阈值电压移动诱导材料可以包括氧化物退火介质层，例如N 2 O 2。 可以在绝缘层上形成阻挡层，可以在阻挡层上形成绝缘层，或者可以在第一绝缘层上形成阻挡层，在隔离层上形成第二绝缘层。 此外，阻挡层可以在形成电容器电极之后或在形成介电层之后形成，例如通过使用差的阶梯覆盖沉积方法。