公开(公告)号：US06767778B2

公开(公告)日：2004-07-27

申请号：US10230809

申请日：2002-08-29

Applicant: Zhongze Wang ,  Inna V. Patrick

Inventor： Zhongze Wang ,  Inna V. Patrick

IPC: H01L218234

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.

Abstract translation: 公开了一种用于通过附加的低剂量超深源极/漏极注入来减少结电容的半导体器件及其制造方法。 特别地，在间隔物形成之后进行超深度注入，以显着降低沟道区中的结电容。

公开(公告)号：US08120109B2

公开(公告)日：2012-02-21

申请号：US10896711

申请日：2004-07-22

Applicant: Zhongze Wang ,  Inna V. Patrick

Inventor： Zhongze Wang ,  Inna V. Patrick

IPC: H01L29/76

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.

Abstract translation: 公开了一种用于通过附加的低剂量超深源极/漏极注入来减少结电容的半导体器件及其制造方法。 特别地，在间隔物形成之后进行超深度注入，以显着降低沟道区中的结电容。

公开(公告)号：US09865330B2

公开(公告)日：2018-01-09

申请号：US12939260

申请日：2010-11-04

Applicant: Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

Inventor： Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

IPC: G11C11/412 ,  H01L27/11

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10T29/49117

Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

公开(公告)号：US09495503B2

公开(公告)日：2016-11-15

申请号：US13372160

申请日：2012-02-13

Applicant: Jeffrey Herbert Fischer ,  Manish Garg ,  Zhongze Wang

Inventor： Jeffrey Herbert Fischer ,  Manish Garg ,  Zhongze Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Abstract translation: 提供了用于在设计和制造集成电路期间进行选择性推送处理以改善集成电路的选定电路的性能的方法和装置。 一种示例性方法包括识别集成电路布局的关键部分，该集成电路布局定义了具有关键工作频率要求的功能元件，并且在关键部分中设计子电路以使能执行速度推动过程以增加子电路的性能。 该方法还可以包括在关键部分和在关键部分之外的集成电路的一部分之间的边界处识别供电节点，时钟供应节点和接口节点中的至少一个。 关键部分可以被设计成具有独立于在关键部分之外的集成电路的部分的功率域。

公开(公告)号：US06984570B2

公开(公告)日：2006-01-10

申请号：US10735355

申请日：2003-12-12

Applicant: Zhongze Wang

Inventor： Zhongze Wang

IPC: H01L21/30

CPC classification number: H01L29/66772 ,  H01L21/76256 ,  H01L29/78603

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

Abstract translation: 形成绝缘体上硅包括集成电路的晶片接合方法包括氮化器件晶片的硅的外表面的至少一部分。 在氮化之后，器件晶片与处理晶片接合。 一种形成绝缘体上硅的方法，包括集成电路包括将包含绝缘体上硅电路的硅层的界面氮化为绝缘体上硅电路的绝缘体层。 在氮化之后，场效应晶体管栅极可靠地形成在包含硅的层上。 公开了其他方法。 无论制造方法如何，都可以考虑集成电路。

公开(公告)号：US06977419B2

公开(公告)日：2005-12-20

申请号：US10931507

申请日：2004-09-01

Applicant: Hongmei Wang ,  Zhongze Wang

Inventor： Hongmei Wang ,  Zhongze Wang

IPC: H01L21/336 ,  H01L29/06

CPC classification number: H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

Abstract: The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

Abstract translation: 本发明提供了一种制造MOSFET中的电介质塞的技术。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及在源极之间的沟道区域 和漏区。

公开(公告)号：US20050151198A1

公开(公告)日：2005-07-14

申请号：US11057302

申请日：2005-02-11

Applicant: Zhongze Wang ,  Chih-Chen Cho

Inventor： Zhongze Wang ,  Chih-Chen Cho

IPC: G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC classification number: G11C11/4125 ,  G11C11/412 ,  H01L21/76885 ,  H01L27/11 ,  H01L27/1104

Abstract: A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.

Abstract translation: 具有金属填充的静态随机存取存储器单元以形成用于增加存储单元的电容的电容器。 更具体地说，一种半导体器件，包括具有形成在该结构的上表面上的上表面和接触表面的结构。 介电材料在接触表面上与第一导电节点和延伸超出电介质材料的第二导电节点形成。 电介质隔板围绕第一和第二导电节点形成，并且导电元件形成在电介质间隔件之间。 导电元件和间隔件形成电容器而不实施附加的掩蔽步骤。

公开(公告)号：US20050003598A1

公开(公告)日：2005-01-06

申请号：US10896711

申请日：2004-07-22

Applicant: Zhongze Wang ,  Inna Patrick

Inventor： Zhongze Wang ,  Inna Patrick

IPC: H01L21/336 ,  H01L21/8234 ,  H01L31/0328

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.

Abstract translation: 公开了一种用于通过附加的低剂量超深源极/漏极注入来减少结电容的半导体器件及其制造方法。 特别地，在间隔物形成之后进行超深度注入，以显着降低沟道区中的结电容。

公开(公告)号：US06808994B1

公开(公告)日：2004-10-26

申请号：US10463159

申请日：2003-06-17

Applicant: Zhongze Wang

Inventor： Zhongze Wang

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78612

Abstract: Source drain on insulator (SDOI) transistors and methods of forming SDOI transistors are described. The SDOI transistors are formed to provide electrical isolation between the body and the channel of the transistor. The electrical isolation comprises either a depletion layer or a p-n junction formed below the SDOI transistor channel region that spans laterally between the SDOI insulators.

Abstract translation: 描述了绝缘体源极漏极（SDOI）晶体管和形成SDOI晶体管的方法。 形成SDOI晶体管，以在主体和晶体管的通道之间提供电隔离。 电隔离包括在SDOI晶体管沟道区域之下形成的耗尽层或p-n结，跨越SDOI绝缘体之间的横向。

公开(公告)号：US06673715B2

公开(公告)日：2004-01-06

申请号：US10002335

申请日：2001-10-24

Applicant: Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

Inventor： Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

IPC: H01L2144

CPC classification number: H01L21/76888 ,  H01L21/76897

Abstract: Methods of forming conductive contacts are described. According to one implementation, the method includes forming a transistor gate structure over a substrate. The gate structure includes a conductive silicide covered by insulative material. A dielectric layer is formed over the substrate and the gate structure. A contact opening is etched into the dielectric layer adjacent the gate structure. After the etching, the substrate is exposed to oxidizing conditions effective to oxidize any conductive silicide within the contact opening which was exposed during the contact opening etch. After the oxidizing, conductive material is formed within the contact opening. According to another embodiment, after the etching, it is determined whether conductive silicide of the gate structure was exposed during the etching. The substrate is then exposed to oxidizing conditions only if conductive silicide of the gate structure was exposed during the etching.