公开(公告)号：US20140011340A1

公开(公告)日：2014-01-09

申请号：US13541957

申请日：2012-07-05

Applicant: Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

Inventor： Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

IPC: H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Abstract translation: 形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。 此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。 不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

公开(公告)号：US20120113708A1

公开(公告)日：2012-05-10

申请号：US12939260

申请日：2010-11-04

Applicant: Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

Inventor： Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

IPC: G11C11/00 ,  H01R43/00

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10T29/49117

Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Abstract translation: 利用独立栅极FinFET架构的稳定SRAM单元提供了诸如读静态噪声余量（RSNM）和写噪声余量（WNM）的器件参数中的常规SRAM单元的改进。 示例性SRAM单元包括一对存储节点，一对位线，一对上拉器件，一对下拉器件和一对通栅器件。 第一控制信号和第二控制信号被配置为调整传递门装置的驱动强度，并且第三控制信号被配置为调节上拉装置的驱动强度，其中第一控制信号被正交地传送到 位线方向，并且第二和第三控制信号沿与位线方向相同的方向路由。 通过在读写操作期间调整上拉和通过栅极器件的驱动强度，RSNM和WNM得到了改进。

公开(公告)号：US20110051535A1

公开(公告)日：2011-03-03

申请号：US12552359

申请日：2009-09-02

Applicant: Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Beom-Mo Han

Inventor： Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Beom-Mo Han

IPC: G11C7/00 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  G11C11/40 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7841 ,  H01L29/7855 ,  H01L29/78648

Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.

Abstract translation: 公开了一种翅片式装置系统和方法。 在特定实施例中，公开了制造晶体管的方法，包括在具有表面的衬底内形成晶体管的栅极，并在衬底内形成掩埋氧化物（BOX）层，并在第一BOX层面 。 该方法还包括形成凸起的源极 - 漏极通道（“鳍”），其中鳍的至少一部分从衬底的表面延伸，并且其中鳍具有邻近第二BOX层的第一鳍面 BOX层。

公开(公告)号：US20100109086A1

公开(公告)日：2010-05-06

申请号：US12266183

申请日：2008-11-06

Applicant: Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Beom-Mo Han

Inventor： Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Beom-Mo Han

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

Abstract translation: 公开了一种使用鳍状场效应晶体管（FINFET）制造半导体的方法。 在特定实施例中，一种方法包括在硅衬底上沉积具有第一侧壁和第二侧壁的第一虚拟结构，所述第一侧壁和第二侧壁被第一宽度分开。 该方法还包括在沉积第一虚拟结构的同​​时在硅衬底上沉积第二虚拟结构。 第二虚拟结构具有分隔第二宽度的第三侧壁和第四侧壁。 第二宽度基本上大于第一宽度。 第一虚拟结构用于形成以大约第一宽度分开的第一对散热片。 第二虚拟结构用于形成分开大约第二宽度的第二对散热片。

公开(公告)号：US20070059874A1

公开(公告)日：2007-03-15

申请号：US11456054

申请日：2006-07-06

Applicant: Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

Inventor： Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.

Abstract translation: 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。 诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。 可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。 可以在形成第一掩模层的公共层中沉积第一离子。 类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。 可以在公共层中沉积第二离子，形成第二掩模层。

公开(公告)号：US07026662B2

公开(公告)日：2006-04-11

申请号：US10740570

申请日：2003-12-22

Applicant: Seung-Chul Song

Inventor： Seung-Chul Song

IPC: H01L33/00

CPC classification number: H01L21/31612 ,  H01L21/02107 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76832

Abstract: A MOSFET device structure and a method of manufacturing the same, in which a photon absorption layer is formed over a gate structure and a substrate in order to avoid plasma induced damage to the gate oxide during high density plasma deposition of a interlayer dielectric layer. The device structure may include an etch stop layer below the photon absorption layer. The photon absorption layer is formed entirely of silicon germanium or it may be a multi-layer formed of a silicon layer and a silicon germanium layer. In the multi-layer structure the silicon germanium layer may be formed on top of the silicon layer or vice-versa. The silicon germanium layer may be formed by implanting germanium ions into a silicon layer or by an epitaxial growth of the silicon germanium alloy layer. In the photon absorption layer the germanium may be substituted by another element whose band gap energy is less than that of silicon.

Abstract translation: MOSFET器件结构及其制造方法，其中在栅极结构和衬底上形成光子吸收层，以便在层间电介质层的高密度等离子体沉积期间避免等离子体对栅极氧化物的损伤。 器件结构可以包括在光子吸收层下面的蚀刻停止层。 光子吸收层完全由硅锗形成，或者它可以是由硅层和硅锗层形成的多层。 在多层结构中，硅锗层可以形成在硅层的顶部上，反之亦然。 硅锗层可以通过将锗离子注入到硅层中或者通过硅锗合金层的外延生长来形成。 在光子吸收层中，锗可以被带隙能量小于硅的另一元素取代。

公开(公告)号：US06501508B1

公开(公告)日：2002-12-31

申请号：US09475132

申请日：1999-12-30

Applicant: Seung Chul Song ,  Dong Il Han ,  Jin Ho Ahn

Inventor： Seung Chul Song ,  Dong Il Han ,  Jin Ho Ahn

IPC: H04N701

CPC classification number: H04N7/0135

Abstract: A vertical video format converter is disclosed including a memory unit which consists of a plurality of line memories to store input video data in one of the line memories, a filter for multiplying video data items respectively output from line memories by coefficients input into corresponding video data item positions and adding the multiplied data items to output filtered data. In the present invention, the position of the filter center value is not fixed, but can be located arbitrarily and the filter coefficients need not be symmetrical. Moreover, an interpolation may be performed by one-time filtering, resulting in faster data processing.

Abstract translation: 公开了一种垂直视频格式转换器，其包括存储单元，该存储器单元由多个行存储器组成，用于将行存储器中的一个存储器中的输入视频数据存储起来;滤波器，用于将输入到行存储器的视频数据项分别输入相应的视频数据 项目位置，并将相乘的数据项添加到输出过滤数据。 在本发明中，滤波器中心值的位置不固定，但可任意定位，滤波器系数不必对称。 此外，可以通过一次性滤波执行插值，导致更快的数据处理。

公开(公告)号：US09865330B2

公开(公告)日：2018-01-09

申请号：US12939260

申请日：2010-11-04

Applicant: Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

Inventor： Seong-Ook Jung ,  Mingu Kang ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Abu-Rahma ,  Beom-Mo Han ,  Lixin Ge ,  Zhongze Wang

IPC: G11C11/412 ,  H01L27/11

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10T29/49117

Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

公开(公告)号：US09337100B2

公开(公告)日：2016-05-10

申请号：US12477412

申请日：2009-06-03

Applicant: Seung-Chul Song ,  Beom-Mo Han ,  Mohamed Hassan Abu-Rahma

Inventor： Seung-Chul Song ,  Beom-Mo Han ,  Mohamed Hassan Abu-Rahma

IPC: H01L21/77 ,  H01L21/8234 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  G03F7/00

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/785 ,  Y10T29/41 ,  Y10T428/24479

Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.

Abstract translation: 公开了一种制造电子设备的装置和方法。 在特定实施例中，装置包括具有压印表面的模板。 压印表面包括具有适于制造鳍状场效应晶体管（FinFET）器件的第一图案的第一区域和具有适于制造平面电子器件的第二图案的第二区域。

公开(公告)号：US20140070327A1

公开(公告)日：2014-03-13

申请号：US13609621

申请日：2012-09-11

Applicant: Hiroaki Niimi ,  Seung-Chul Song

Inventor： Hiroaki Niimi ,  Seung-Chul Song

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928

Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

Abstract translation: 互补金属氧化物半导体（CMOS）集成电路结构及其替代金属栅极工艺的制造方法。 P沟道和n沟道MOS晶体管由组成或厚度彼此不同的高k栅介质材料形成，并且在组成或厚度上彼此不同的界面电介质材料形成。 所描述的替代栅极处理使得能够构造，使得p沟道或n沟道晶体管栅极结构都不包括来自另一个晶体管的金属栅极材料，从而有助于用填充金属可靠地填充栅极结构。