公开(公告)号：US09040950B2

公开(公告)日：2015-05-26

申请号：US13225926

申请日：2011-09-06

申请人： Kouji Matsuo

发明人： Kouji Matsuo

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146

摘要： According to one embodiment, a nonvolatile memory device includes a first interconnect, an insulating layer, a needle-like metal oxide, and a second interconnect. The insulating layer is provided on the first interconnect. The needle-like metal oxide pierces the insulating layer in a vertical direction. The second interconnect is provided on the insulating layer.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一互连，绝缘层，针状金属氧化物和第二互连。 绝缘层设置在第一互连上。 针状金属氧化物在垂直方向上穿透绝缘层。 第二互连设置在绝缘层上。

公开(公告)号：US08138552B2

公开(公告)日：2012-03-20

申请号：US12338641

申请日：2008-12-18

申请人： Kouji Matsuo

发明人： Kouji Matsuo

IPC分类号： H01L21/70

CPC分类号： H01L29/66545 ,  H01L29/0843 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate electrode, and stress application layers embedded in source and drain regions located, on a surface of the substrate, at a position which sandwiches the gate electrode, and applying stress to a channel region located under the gate insulation film in the substrate, a height of upper ends of interfaces between the substrate and the stress application layers being higher than a height of a lower end of an interface between the substrate and the gate insulation film.

摘要翻译： 根据本发明的实施例的半导体器件包括：基板，形成在基板上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极，设置在栅电极的侧表面上的侧壁绝缘膜，以及应力施加层 嵌入在基板的表面上的源极和漏极区域中，夹着所述栅电极的位置，并对位于所述基板的栅极绝缘膜下方的沟道区域施加应力， 衬底和应力施加层高于衬底和栅极绝缘膜之间的界面的下端的高度。

公开(公告)号：US20110303958A1

公开(公告)日：2011-12-15

申请号：US13156702

申请日：2011-06-09

申请人： Kouji MATSUO ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

发明人： Kouji MATSUO ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

IPC分类号： H01L29/792 ,  H03K19/08 ,  H01L21/336

CPC分类号： H01L29/7926 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/24

摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层 在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线， 选择栅极线上的第二个方向。 选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。 每条字线通常连接到沿第二方向布置的控制门。

公开(公告)号：US07772076B2

公开(公告)日：2010-08-10

申请号：US11715965

申请日：2007-03-09

申请人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

发明人： Atsushi Yagishita ,  Kouji Matsuo ,  Yasushi Akasaka ,  Kyoichi Suguro ,  Yoshitaka Tsunashima

IPC分类号： H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1033 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/926

摘要： A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.

摘要翻译： 一种制造半导体器件的方法包括在衬底的一个主表面的第一区域上形成具有侧表面和上表面的虚拟栅极布线层，所述衬底的主表面包括第一区域和第二区域，之后 通过使用外延生长在所述衬底的主表面的第二区域上形成半导体膜，所述半导体膜的厚度小于所述虚拟栅极布线层的厚度，并且在所述半导体膜上形成栅极侧壁，所述栅极侧壁 由绝缘体制成并覆盖虚拟栅极布线层的侧表面。

公开(公告)号：US20100072550A1

公开(公告)日：2010-03-25

申请号：US12591643

申请日：2009-11-25

申请人： Kouji Matsuo

发明人： Kouji Matsuo

IPC分类号： H01L27/12 ,  H01L27/088

CPC分类号： H01L29/42384 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs.

公开(公告)号：US07642162B2

公开(公告)日：2010-01-05

申请号：US11898020

申请日：2007-09-07

申请人： Kouji Matsuo

发明人： Kouji Matsuo

IPC分类号： H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs.

摘要翻译： 半导体器件具有用于分开形成在半导体衬底上的行中的多个MOSFET的多个柱状栅极电极和形成在多个柱状栅电极的相邻的两个柱状栅电极之间的部分中以形成沟道的半导体区域 MOSFET。

公开(公告)号：US07602013B2

公开(公告)日：2009-10-13

申请号：US11649752

申请日：2007-01-05

申请人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Kouji Matsuo

发明人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Kouji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/66621

摘要： A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening. It is possible to provide a semiconductor device and a manufacturing method of the same which realize easy control of a recess amount and reduction in damage at the time of the recessing.

摘要翻译： 半导体器件包括：设置在半导体衬底上或上方的具有开口并且包含Si和Ge的层; 以及设置在与开口相对应的位置处的门。 可以提供一种半导体器件及其制造方法，其实现容易控制凹陷量并减少凹陷时的损伤。

公开(公告)号：US07461538B2

公开(公告)日：2008-12-09

申请号：US10571785

申请日：2004-09-13

申请人： Kouji Matsuo ,  Satoshi Ishikawa

发明人： Kouji Matsuo ,  Satoshi Ishikawa

IPC分类号： G01N7/00

CPC分类号： G01N27/407 ,  G01N27/4062 ,  G01N27/4077

摘要： The present invention provides a sensor capable of maintaining an electrical connection between the lead frame and an electrode terminal section of the detection element even when an inadequate external force is applied to a lead frame and a sensor production method capable of preventing the lead frame from buckling and being deformed into an inadequate shape. The lead frame (second lead frame) can inhibit movement of a second frame main body section axially toward a rear end side through engagement of a third locking surface of a second locking section with a second locking groove and can inhibit the second frame main body section from going apart from an inner surface of an insertion hole through engagement of a fourth locking surface of the second frame locking section, which faces an element engagement section side. Namely, even when an external force is applied to the lead frame, movement of the lead frame main body section (second lead frame main body section) can be inhibited and a variation in the relative positions of the lead frame and the detection element can be prevented.

摘要翻译： 本发明提供了一种能够在引线框架和检测元件的电极端子部分之间保持电连接的传感器，即使当对引线框架施加不充分的外力时，还能够防止引线框架屈曲 并变形为不适当的形状。 引线框架（第二引线框架）可以通过第二锁定部分的第三锁定表面与第二锁定槽的接合来阻止第二框架主体部分沿着后端侧的移动，并且可以禁止第二框架主体部分 通过与第二框架锁定部分的面向元件接合部分侧的第四锁定表面的接合而从插入孔的内表面分离。 也就是说，即使当引线框架施加外力时，也可以禁止引线框架主体部分（第二引线框架主体部分）的移动，并且引线框架和检测元件的相对位置的变化可以是 防止了

公开(公告)号：US07459246B2

公开(公告)日：2008-12-02

申请号：US11648564

申请日：2007-01-03

申请人： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

发明人： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

IPC分类号： G03F9/00

CPC分类号： B82Y10/00 ,  C23C14/042 ,  C23C14/48 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01L21/266 ,  Y10T428/24273

摘要： Preparing a stencil mask comprising a silicon thin film in which an opening for selectively irradiating charged particles to a semiconductor substrate is provided and whose irradiation surface on which the charged particles are irradiated is implanted with an impurity, and selectively irradiating charged particles to the semiconductor substrate using the stencil mask which is opposingly arranged on the semiconductor substrate.

摘要翻译： 制备包括硅薄膜的模板掩模，其中用于选择性地将带电粒子照射到半导体基板的开口，并且其上照射有带电粒子的照射面被注入杂质，并且将带电粒子选择性地照射到半导体衬底 使用相对设置在半导体衬底上的模板掩模。

公开(公告)号：US20070096615A1

公开(公告)日：2007-05-03

申请号：US10571764

申请日：2004-09-13

申请人： Kouji Matsuo ,  Satoshi Ishikawa

发明人： Kouji Matsuo ,  Satoshi Ishikawa

IPC分类号： H01T13/20

CPC分类号： G01N27/407 ,  G01N27/4062 ,  G01N27/4077

摘要： The present invention provides a sensor and a method of producing the same, which makes an electrical connection condition between an electrode terminal section of a detection element and a metallic terminal member good. The sensor includes a lead frame (metallic terminal member) that changes a support condition of supporting an element abutment section for contact with a detection element on a frame main body section, into a one-point support or a two-point support. At a first-half stage of a work for assembly of the lead frame and the detection element, the element abutment section is put in a one-point support condition relative to the frame main body section and the lead frame produces a relatively smaller resilient force, such that it becomes possible to prevent an excessively large pressure from being applied to the detection element. After the assembly work is completed, the element abutment section is put in a two-point support condition relative to the frame main body section and the lead frame produces a larger resilient force as compared with that in the one-point support condition, such that the electrical connection condition between the lead frame and the detection element can be good.

摘要翻译： 本发明提供一种传感器及其制造方法，其使得检测元件的电极端子部和金属端子部件之间的电连接状态良好。 传感器包括引导框架（金属端子构件），其将支撑用于与框架主体部分上的检测元件接触的元件抵接部的支撑状态改变为一点支撑或两点支撑。 在引线框架和检测元件的组装工作的前半段，元件抵接部分相对于框架主体部分处于一点支撑状态，并且引线框架产生相对较小的弹性力 ，使得可以防止对检测元件施加过大的压力。 在组装工作完成之后，元件抵接部分相对于框架主体部分处于两点支撑状态，并且与一点支撑状态相比，引线框架产生较大的弹性力，使得 引线框架和检测元件之间的电连接状态可以很好。