公开(公告)号：US08633535B2

公开(公告)日：2014-01-21

申请号：US13156702

申请日：2011-06-09

申请人： Kouji Matsuo ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

发明人： Kouji Matsuo ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/24

摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层 在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线， 选择栅极线上的第二个方向。 选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。 每条字线通常连接到沿第二方向布置的控制门。

公开(公告)号：US08569825B2

公开(公告)日：2013-10-29

申请号：US12881510

申请日：2010-09-14

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件的制造方法包括：在半导体衬底上形成多个结构，所述多个结构中的每个结构使得在多个第一半导体膜和多个第一半导体膜的叠层膜中 的第二半导体膜交替堆叠，至少第二半导体膜经由栅极电介质膜被半导体或导体柱构件保持; 选择性地从层叠膜去除第一半导体膜，同时保持第二半导体膜由用于每个结构的柱构件保持的状态; 在除去第一半导体膜之后对每个结构氧化暴露的表面; 以及在暴露表面被氧化的多个结构之间嵌入层间电介质膜。

公开(公告)号：US20110233645A1

公开(公告)日：2011-09-29

申请号：US12881510

申请日：2010-09-14

申请人： Toshihiko IINUMA

发明人： Toshihiko IINUMA

IPC分类号： H01L29/792 ,  H01L21/20

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件的制造方法包括：在半导体衬底上形成多个结构，所述多个结构中的每个结构使得在多个第一半导体膜和多个第一半导体膜的叠层膜中 的第二半导体膜交替堆叠，至少第二半导体膜经由栅极电介质膜被半导体或导体柱构件保持; 选择性地从层叠膜去除第一半导体膜，同时保持第二半导体膜由用于每个结构的柱构件保持的状态; 在除去第一半导体膜之后对每个结构氧化暴露的表面; 以及在暴露表面被氧化的多个结构之间嵌入层间电介质膜。

公开(公告)号：US07964906B2

公开(公告)日：2011-06-21

申请号：US11873745

申请日：2007-10-17

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A semiconductor device has a semiconductor layer, a plurality of charge-accumulating layers formed at a predetermined interval from each other on said semiconductor layer through a first insulating film, a second insulating film formed on said charge-accumulating layer, a control gate including a silicide film formed on said second insulating film, a third insulating film formed between said control gates so that the top surface of said third insulating film is lower than the top surface of said control gate but is higher than the top surface of said second insulating film, a fourth insulating film formed into a concave shape so as to cover the top surface of said third insulating film and the side surfaces of said control gate positioned higher than the top surface of said third insulating film, and a fifth insulating film formed on said control gate and said fourth insulating film.

摘要翻译： 半导体器件具有半导体层，通过第一绝缘膜在所述半导体层上以预定间隔彼此形成的多个电荷累积层，形成在所述电荷累积层上的第二绝缘膜，包括 形成在所述第二绝缘膜上的硅化物膜，形成在所述控制栅极之间的第三绝缘膜，使得所述第三绝缘膜的顶表面比所述控制栅极的顶表面低，但高于所述第二绝缘膜的顶表面 形成为覆盖所述第三绝缘膜的上表面的第四绝缘膜和位于所述第三绝缘膜的上表面以上的所述控制栅极的侧面的第四绝缘膜，以及形成在所述第三绝缘膜上的第五绝缘膜 控制栅极和所述第四绝缘膜。

公开(公告)号：US07825433B2

公开(公告)日：2010-11-02

申请号：US11898602

申请日：2007-09-13

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L27/088

CPC分类号： H01L29/665 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

摘要： A semiconductor device having a silicide film above source-drain regions comprises an element isolation insulating film which is provided so as to enclose an element forming region of a semiconductor substrate whose main component is silicon and contains silicon oxide as a main component, a gate electrode which is formed above the element forming region via a gate insulating film, diffused layers which are formed in the semiconductor substrate so as to sandwich a channel region below the gate electrode, semiconductor regions which are formed so as to sandwich the channel region and diffused regions and are composed of semiconductor material whose lattice constant differs from that of silicon, a silicon nitride film which is formed between the semiconductor regions and the element isolation insulating film and above the lowest part of the semiconductor regions, and a conducting film which is formed at the surface of the semiconductor regions.

摘要翻译： 具有源极 - 漏极区以上的硅化物膜的半导体器件包括元件隔离绝缘膜，该元件隔离绝缘膜被设置为包围主要成分为硅并且含有氧化硅作为主要成分的半导体衬底的元件形成区域，栅电极 其通过栅极绝缘膜形成在元件形成区域的上方，形成在半导体衬底中以将沟道区域夹在栅电极下方的扩散层，形成为夹着沟道区域和扩散区域的半导体区域 并且由半导体材料构成，其晶格常数不同于硅，氮化硅膜形成在半导体区域和元件隔离绝缘膜之间并位于半导体区域的最下部，并且形成在 半导体区域的表面。

公开(公告)号：US07768094B2

公开(公告)日：2010-08-03

申请号：US11220716

申请日：2005-09-08

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L23/58

CPC分类号： H01L27/11 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1116 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor integrated circuit includes a rectangular low speed circuit area including a low speed circuit comprising a low speed transistor having a first source extension region and a first drain extension region, and a rectangular high speed circuit area adjacent to the low speed circuit area and including a high speed circuit comprising a high speed transistor having a second source extension region and a second drain extension region thinner than the first source and drain extension regions.

摘要翻译： 一种半导体集成电路包括：包括低速电路的矩形低速电路区域，该低速电路包括具有第一源延伸区域和第一漏极延伸区域的低速晶体管和与低速电路区域相邻的矩形高速电路区域，并且包括 高速电路包括具有比第一源极和漏极延伸区域薄的第二源极延伸区域和第二漏极延伸区域的高速晶体管。

公开(公告)号：US07741220B2

公开(公告)日：2010-06-22

申请号：US12081439

申请日：2008-04-16

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

摘要翻译： 本发明公开了即使小型化也能提高其特性的半导体器件及其制造方法。 根据本发明的一个方面，提供了一种半导体器件，包括：第一半导体元件器件，包括形成在半导体衬底中的一对第一扩散层，其间具有第一栅电极;第一导体层，形成在第一扩散部 层，并且在第一方向上具有内部应力;以及第二半导体元件器件，其包括形成在所述半导体衬底中的一对第二扩散层，其间具有第二栅电极，以及形成在所述第二扩散层中的第二导体层， 在与第一方向相反的第二方向上的内部应力，并且由与第一导体层相同的元件构成。

公开(公告)号：US20090065844A1

公开(公告)日：2009-03-12

申请号：US12204539

申请日：2008-09-04

申请人： Toshihiko IINUMA

发明人： Toshihiko IINUMA

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells each having a double-layered gate structure in which a floating gate and a control gate formed of a nickel silicide film are laminated, a first contact plug formed on a substrate contact portion of a surface of the semiconductor substrate, the first contact plug having a lower layer formed of a semiconductor film and an upper layer formed of a nickel silicide film, and second contact plugs formed on the control gates and first contact plug.

摘要翻译： 非易失性半导体存储器件包括多个非易失性存储单元，每个非易失性存储单元具有双层栅极结构，其中浮置栅极和由硅化镍膜形成的控制栅极层叠，第一接触插塞形成在基板接触部分上 半导体衬底的表面，具有由半导体膜形成的下层的第一接触插塞和由硅化镍膜形成的上层，以及形成在控制栅极和第一接触插塞上的第二接触插塞。

公开(公告)号：US07242064B2

公开(公告)日：2007-07-10

申请号：US10810837

申请日：2004-03-29

申请人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

发明人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/78609

摘要： In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

摘要翻译： 在半导体器件中，形成在半导体衬底上的MISFET的栅极电连接到MISFET的沟道下方的阱区，MISFET形成在形成在半导体衬底上的岛状元件区域中，并且电气 MISFET的栅电极和半导体衬底中的阱区之间的连接在岛状元件区域的侧表面上进行。

公开(公告)号：US20070066001A1

公开(公告)日：2007-03-22

申请号：US11340517

申请日：2006-01-27

申请人： Toshihiko Iinuma

发明人： Toshihiko Iinuma

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

摘要翻译： 本发明公开了即使小型化也能提高其特性的半导体器件及其制造方法。 根据本发明的一个方面，提供了一种半导体器件，包括：第一半导体元件器件，包括形成在半导体衬底中的一对第一扩散层，其间具有第一栅电极;第一导体层，形成在第一扩散部 层，并且在第一方向上具有内部应力;以及第二半导体元件器件，其包括形成在所述半导体衬底中的一对第二扩散层，其间具有第二栅电极，以及形成在所述第二扩散层中的第二导体层， 在与第一方向相反的第二方向上的内部应力，并且由与第一导体层相同的元件构成。