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    Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance
    3.
    发明授权
    Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance 失效
    具有工程变更布线和分布式去耦电容的半导体芯片插入模块

    公开(公告)号：US5177594A

    公开(公告)日：1993-01-05

    申请号：US807802

    申请日：1991-12-13

    申请人： Dudley A. Chance ,  Evan E. Davidson ,  Timothy R. Dinger ,  David B. Goland ,  David P. Lapotin

    发明人： Dudley A. Chance ,  Evan E. Davidson ,  Timothy R. Dinger ,  David B. Goland ,  David P. Lapotin

    IPC分类号： H01L23/498 ,  H01L23/64 ,  H01L25/065

    CPC分类号： H01L23/642 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312

    摘要： A semiconductor package is described for supporting and interconnecting semiconductor chips, each chip having contact lands on a contact surface, the package also including a substrate with a contact surface. An interposer module is disposed between at least one chip's contact surface and the substrate's contact surface. The interposer module has first and second opposed surfaces and a first plurality of contact locations positioned on its first surface which mate with a chip's contact land. A second plurality of contact locations on the interposer modules second surface are positioned to mate with contact lands on the substrate. A set of conductive vias are positioned within the interposer module and connect the first plurality of contact locations with a first subset of the second plurality of contact locations. A distributed capacitance layer is positioned within the interposer and is adjacent to its first surface. Adjacent to the second surface are X and Y lines which can be used to make engineering change interconnections.

    摘要翻译： 描述了用于支撑和互连半导体芯片的半导体封装，每个芯片在接触表面上具有接触焊盘，该封装还包括具有接触表面的衬底。 插入器模块设置在至少一个芯片的接触表面和基板的接触表面之间。 插入器模块具有第一和第二相对表面和位于其第一表面上的第一多个接触位置，其与芯片的接触区域配合。 位于插入器模块第二表面上的第二多个接触位置以与衬底上的接触焊盘配合。 一组导电通孔定位在插入器模块内并且将第一多个接触位置与第二多个接触位置的第一子集连接。 分布式电容层位于插入器内并与其第一表面相邻。 与第二表面相邻的是X和Y线，可用于制造工程变更互连。

    Hermetic package for an electronic device and method of manufacturing same
    4.
    发明授权
    Hermetic package for an electronic device and method of manufacturing same 失效
    用于电子设备的密封包装及其制造方法

    公开(公告)号：US5169310A

    公开(公告)日：1992-12-08

    申请号：US757863

    申请日：1991-09-11

    申请人： Dudley A. Chance ,  David B. Goland ,  Ho-Ming Tong

    发明人： Dudley A. Chance ,  David B. Goland ,  Ho-Ming Tong

    IPC分类号： H01L21/48 ,  H01L21/50

    CPC分类号： H01L21/50 ,  H01L21/4807 ,  H01L21/486

    摘要： A hermetic package for an electronic device is manufactured by providing a green glass ceramic body with a green via to produce a workpiece. The workpiece is sintered at a temperature at or above 500.degree. C., while compressing the workpiece at a pressure at or above 100 pounds per square inch, so as to obtain a hermetic package. The green via comprises a mixture of copper and a glass ceramic material with a sufficient volume of glass to produce a hermetic package, yet with sufficient copper to have a suitable electrical conductivity.The hermetic package thus produced comprises a sintered glass ceramic body having an electrically conductive sintered via which is hermetically bonded to the glass ceramic body and which comprises a mixture of an electrically conductive material and a glass ceramic material. The electrically conductive material forms at most 50 volume percent of the via.The workpeice may be sintered in a sintering fixture having a frame and a compensating insert. The compensating insert and frame bound a sintering chamber for accommodating the workpiece. By providing a frame having a thermal expansion coefficient greater than that of the workpiece, and by providing a compensating insert having a thermal expansion coefficient greater than that of the frame, a close fit can be assured between the workpiece and the sintering fixture over a large range of temperatures.

    摘要翻译： 通过提供具有绿色通孔的绿色玻璃陶瓷体以制造工件来制造用于电子设备的气密封装。 将工件在等于或高于500℃的温度下烧结，同时在100磅/平方英寸的压力下压缩工件，以获得气密封装。 绿色通孔包括具有足够体积的玻璃的铜和玻璃陶瓷材料的混合物以产生气密封装，但是具有足够的铜以具有合适的导电性。 如此制造的密封包装包括具有导电烧结通孔的烧结玻璃陶瓷体，其通过气密地结合到玻璃陶瓷体并且包括导电材料和玻璃陶瓷材料的混合物。 导电材料形成通孔的至多50体积％。 工件可以在具有框架和补偿插入件的烧结夹具中烧结。 补偿插入物和框架结合用于容纳工件的烧结室。 通过提供具有大于工件的热膨胀系数的热膨胀系数的框架，并且通过提供具有大于框架的热膨胀系数的热膨胀系数的补偿插入件，可以在大的工件和烧结夹具之间确保紧密配合 温度范围

    Method for making punches using multi-layer ceramic technology
    5.
    发明授权
    Method for making punches using multi-layer ceramic technology 失效
    使用多层陶瓷技术制作冲孔的方法

    公开(公告)号：US06352014B1

    公开(公告)日：2002-03-05

    申请号：US09464510

    申请日：1999-12-15

    申请人： David B. Goland ,  David C. Long ,  John U. Knickerbocker ,  Subhash L. Shinde

    发明人： David B. Goland ,  David C. Long ,  John U. Knickerbocker ,  Subhash L. Shinde

    IPC分类号： B26F114

    CPC分类号： B26F1/14 ,  B23P15/24 ,  B26F2210/08 ,  H05K1/0306 ,  H05K3/005 ,  Y10T83/9423

    摘要： A method for making small punches by employing multi-layer ceramic (MLC) technology includes the steps of preparing a sublaminate matrix of a high or low sintering temperature material, drilling holes in the sublaminate using a mask as a guide, filling the holes with punch material paste by a solupor process, laminating the sublaminate to a base plate or as a freestanding substrate, firing a laminate at an appropriate sintering temperature and removing the matrix material by a chemical or mechanical method. In accordance with the present invention, a large number of small punches are made in parallel to precise dimensions of two to ten mils in diameter and approximately 100 mils in length. This method allows that a punch plate array can also be used to simultaneously punch an array of vias in a greensheet and eliminates the additional step of loading individual punches into a punch plate, offering cost and time savings.

    摘要翻译： 通过采用多层陶瓷（MLC）技术制造小冲孔的方法包括以下步骤：制备高或低烧结温度材料的层压基质，使用掩模作为导向孔在该层压板上钻孔，用冲孔 通过溶剂法处理材料糊料，将层压材料层压到基板或独立的基材上，在适当的烧结温度下焙烧层压材料，并通过化学或机械方法除去基体材料。 根据本发明，大量的小冲头与直径为2至10密耳，长度为大约100密耳的精确尺寸并联制成。 该方法允许冲压板阵列也可以用于同时冲切毛坯中的通孔阵列，并且消除了将单个冲头加载到冲压板中的额外步骤，从而节约了成本和时间。

    Supersaturation method for producing metal powder with a uniform distribution of dispersants method of uses thereof and structures fabricated therewith
    10.
    发明授权
    Supersaturation method for producing metal powder with a uniform distribution of dispersants method of uses thereof and structures fabricated therewith 失效
    用于生产分散剂均匀分布的金属粉末的使用方法和用其制造的结构的过饱和方法

    公开(公告)号：US5292477A

    公开(公告)日：1994-03-08

    申请号：US965149

    申请日：1992-10-22

    申请人： Dudley A. Chance ,  David B. Goland ,  Srinivasa S. N. Reddy ,  Subhash L. Shinde ,  Donald R. Wall

    发明人： Dudley A. Chance ,  David B. Goland ,  Srinivasa S. N. Reddy ,  Subhash L. Shinde ,  Donald R. Wall

    IPC分类号： H01L23/13 ,  C22C1/04 ,  H01L23/12 ,  H01L23/15 ,  H01L23/498 ,  B22F7/00

    CPC分类号： C22C1/0466 ,  C22C1/0425 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701

    摘要： Methods of fabricating powders of electrically conductive particles supersaturated with grain growth control additives are described. A molten admixture of an electrically conductive material and a grain growth control additive is atomized by spraying an inert atmosphere forming fine molten particles which rapidly cool to form solid particles which are supersaturated with the grain growth control additive. The supersaturated particles are heated to form an electrical conductor having grain sizes less than about 25 microns. The supersaturated particles can be combined with a binder to form an electrical conductor forming paste. Patterns of the paste can be embedded in a green ceramic which can be sintered to form a semiconductor chip packaging substrate having electrical conductors with controlled grain size. During sintering of the combination of ceramic precursor and conductor forming paste, the grain growth control additive results in a substantially void free and crack free via filled with metal having a fine grain morphology.

    摘要翻译： 描述了用晶粒生长控制添加剂过饱和的导电颗粒的粉末的制造方法。 导电材料和晶粒生长控制添加剂的熔融混合物通过喷雾形成精细熔融颗粒的惰性气氛而雾化，其迅速冷却以形成与晶粒生长控制添加剂过饱和的固体颗粒。 过饱和颗粒被加热以形成具有小于约25微米的颗粒尺寸的电导体。 过饱和颗粒可与粘合剂组合以形成电导体形成浆料。 糊状物的图案可以嵌入生坯陶瓷中，该陶瓷可以被烧结以形成具有受控晶粒尺寸的电导体的半导体芯片封装基板。 在陶瓷前体和导体形成膏的组合的烧结期间，晶粒生长控制添加剂通过填充有具有细晶粒形态的金属而导致基本上无空隙和无裂纹。