公开(公告)号：US08395051B2

公开(公告)日：2013-03-12

申请号：US12317598

申请日：2008-12-23

申请人： Mengzhi Pang ,  Charan Gurumurthy

发明人： Mengzhi Pang ,  Charan Gurumurthy

IPC分类号： H05K1/09 ,  B23K31/02 ,  H05K7/10

CPC分类号： H05K3/3463 ,  B23K35/262 ,  B23K35/3033 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/11849 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/19043

摘要： Methods of forming a microelectronic structure are described. Those methods include doping a lead free solder material with nickel, wherein the nickel comprises up to about 0.2 percent by weight of the solder material, and then applying the solder material to a substrate comprising a copper pad.

摘要翻译： 描述形成微电子结构的方法。 这些方法包括用镍掺杂无铅焊料材料，其中镍包含至多约0.2重量％的焊料材料，然后将焊料材料施加到包括铜焊盘的衬底上。

公开(公告)号：US08353101B2

公开(公告)日：2013-01-15

申请号：US13008849

申请日：2011-01-18

申请人： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

发明人： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

IPC分类号： H05K3/00 ,  H01L21/46

CPC分类号： H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

摘要： An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

摘要翻译： 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US08115307B2

公开(公告)日：2012-02-14

申请号：US12540265

申请日：2009-08-12

申请人： Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

发明人： Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

IPC分类号： H01L23/12

CPC分类号： H05K1/183 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H01L2224/05599

摘要： An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.

摘要翻译： 本发明的实施例是减少设备之间的互连长度的技术。 在具有基板表面的基板中形成空腔。 空腔有一个深度。 具有器件表面和厚度的第一器件被放置在腔中。 厚度与深度匹配，使得器件表面与衬底表面近似平面。 第一设备通过第二设备上的凸块附接到第二设备。

公开(公告)号：US20100044862A1

公开(公告)日：2010-02-25

申请号：US12195339

申请日：2008-08-20

申请人： Ravi Nalla ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Ravi Nalla ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H05K3/243 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3025 ,  H05K3/28 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/054

摘要： A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

摘要翻译： 提供一种在半导体衬底上形成崩溃芯片连接凸块的方法。 该方法包括提供半导体衬底，该半导体衬底在半导体衬底的顶表面上具有多个凸块通孔，并且电镀多个凸点通孔以在半导体衬底的顶表面上形成多个通孔焊盘。 该方法还包括在半导体衬底的顶表面上设置多个焊料微球，其中每个焊料微球放置在半导体衬底上的相应的通孔焊盘上并回流多个焊料微球以在其上形成塌陷芯片连接凸块 半导体衬底。

公开(公告)号：US20090238233A1

公开(公告)日：2009-09-24

申请号：US12052650

申请日：2008-03-20

申请人： Omar Bchir ,  Islam Salama ,  Charan Gurumurthy ,  Houssam Jomaa ,  Ravi Nalla

发明人： Omar Bchir ,  Islam Salama ,  Charan Gurumurthy ,  Houssam Jomaa ,  Ravi Nalla

IPC分类号： H01S5/026 ,  H01L33/00 ,  H01L31/12 ,  H01L31/18

CPC分类号： G02B6/02042 ,  H01L31/0203 ,  H01S5/02248 ,  H01S5/02284 ,  H01S5/423

摘要： Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

摘要翻译： 通常描述光学晶粒结构和相关的封装衬底。 在一个示例中，电子设备包括封装衬底，其具有封装衬底芯，与封装衬底芯耦合的电介质层，以及与封装衬底芯耦合的一个或多个输入/输出（I / O）光纤或与 所述积聚介质层或其组合，所述一个或多个I / O光纤以将I / O光信号引导到所述封装基板，其中所述一个或多个I / O光纤允许输入和输出光信号 穿过一个或多个I / O光纤。

公开(公告)号：US20090166858A1

公开(公告)日：2009-07-02

申请号：US11966876

申请日：2007-12-28

申请人： Omar J. Bchir ,  Munehiro Toyama ,  Charan Gurumurthy ,  Tamil Selvy Selvamuniandy

发明人： Omar J. Bchir ,  Munehiro Toyama ,  Charan Gurumurthy ,  Tamil Selvy Selvamuniandy

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L23/49811 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/244 ,  H05K3/4602 ,  H01L2924/00

摘要： An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.

摘要翻译： LGA衬底包括具有积聚电介质材料（150），至少一个金属层（125）和形成在其上的阻焊剂（155）的芯体（110），导电焊盘栅极阵列焊盘（120）电连接 在金属层上，导电焊盘栅格阵列焊盘上的镍层（121），镍层上的钯层（122）和钯层上的金层（123）。

公开(公告)号：US20090108455A1

公开(公告)日：2009-04-30

申请号：US11923194

申请日：2007-10-24

申请人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

发明人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

摘要翻译： 公开了一种用于制造集成电路（IC）的工艺和由此形成的IC。 该方法包括提供基底。 该方法还包括在衬底中形成多个纵向沟槽，并在多个纵向沟槽的至少一个纵向沟槽上沉积第一导电材料层。 第一导电材料层的第一层沉积在第一导电材料的层上。 此后，该方法包括在第二导电材料的第一层上沉积第二导电材料层。 第二导电材料的第二层至少部分地填充至少一个纵向沟槽。 选择第一导电材料使得第一导电材料的还原电位小于第二导电材料的还原电位。

公开(公告)号：US08440916B2

公开(公告)日：2013-05-14

申请号：US11769900

申请日：2007-06-28

申请人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H05K1/11

CPC分类号： H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/426 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

摘要翻译： 制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二补充图案化导电层提供到第一和第二辅助绝缘层的相应的一个上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层 其中。

公开(公告)号：US20110290864A1

公开(公告)日：2011-12-01

申请号：US13205606

申请日：2011-08-08

申请人： Mengzhi PANG ,  Liu Pilin ,  Charan GURUMURTHY

发明人： Mengzhi PANG ,  Liu Pilin ,  Charan GURUMURTHY

IPC分类号： B23K1/20

CPC分类号： B23K35/262 ,  B23K2101/36 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/14 ,  Y10T428/12708 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01027 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

摘要翻译： 描述在电子组件中使用的电子组件和焊料。 一个实施例包括管芯和衬底，其中焊料材料位于管芯和衬底之间，焊料包含至少91重量％的Sn，0.4至1.0重量％的Cu和至少一种掺杂剂，其选自Ag， Bi，P和Co.描述和要求保护其它实施例。

公开(公告)号：US07985622B2

公开(公告)日：2011-07-26

申请号：US12195339

申请日：2008-08-20

申请人： Ravi Nalla ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

发明人： Ravi Nalla ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC分类号： H01L21/44 ,  B23K31/00

CPC分类号： H05K3/243 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3025 ,  H05K3/28 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/054

摘要： A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

摘要翻译： 提供一种在半导体衬底上形成崩溃芯片连接凸块的方法。 该方法包括提供半导体衬底，该半导体衬底在半导体衬底的顶表面上具有多个凸块通孔，并且电镀多个凸点通孔以在半导体衬底的顶表面上形成多个通孔焊盘。 该方法还包括在半导体衬底的顶表面上设置多个焊料微球，其中每个焊料微球放置在半导体衬底上的相应的通孔焊盘上并回流多个焊料微球以在其上形成塌陷芯片连接凸块 半导体衬底。