公开(公告)号：US09941158B2

公开(公告)日：2018-04-10

申请号：US13211062

申请日：2011-08-16

Applicant: Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

Inventor： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288

CPC classification number: H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

公开(公告)号：US20130147043A1

公开(公告)日：2013-06-13

申请号：US13757153

申请日：2013-02-01

Applicant: Javier Soto Gonzalez ,  Houssam Jomaa

Inventor： Javier Soto Gonzalez ,  Houssam Jomaa

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/06 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/20 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/8385 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Abstract translation: 描述了具有嵌入式堆叠的通过硅通孔的衬底的衬底。 例如，一种装置包括第一模具和第二模具。 第二管芯具有设置在其中的一个或多个穿硅通孔（TSV管芯）。 第一管芯通过一个或多个穿硅通孔电耦合到TSV管芯。 该设备还包括无芯基板。 第一芯片和TSV芯片都嵌入在无芯基板中。

公开(公告)号：US07909977B2

公开(公告)日：2011-03-22

申请号：US12056985

申请日：2008-03-27

Applicant: Houssam Jomaa ,  Amruthavalli P. Alur ,  Dilan Seneviratne

Inventor： Houssam Jomaa ,  Amruthavalli P. Alur ,  Dilan Seneviratne

IPC: C25D5/34

CPC classification number: H05K3/387 ,  H05K3/0032 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/465 ,  H05K3/4661 ,  H05K2203/066 ,  H05K2203/1152 ,  H05K2203/1383 ,  Y10T428/24355 ,  Y10T428/24612

Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.

Abstract translation: 一种制造用于微电子器件的衬底的方法包括提供作为衬底的堆积层的电介质材料（120,220,920），将底漆（140,240,940）施加到表面（121,221， 921），并且在引物上形成导电层（150,250,950）。 在另一个实施方案中，该方法包括提供电介质材料，形成延伸到电介质材料中的特征，在电介质材料上形成导电层，将引物施加到导电层的表面，并附着电介质层（960） 到底漆。

公开(公告)号：US20090084598A1

公开(公告)日：2009-04-02

申请号：US11865261

申请日：2007-10-01

Applicant: Houssam Jomaa

Inventor： Houssam Jomaa

IPC: H05K3/10 ,  H05K1/11

CPC classification number: H05K3/4682 ,  H05K1/113 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0571 ,  H05K2203/0733

Abstract: Disclosed are a coreless substrate and a method of manufacturing the same. The coreless substrate includes a solder resist layer capable of being formed on each of on a first side and a second side of a metal panel. The solder resist layer includes at least one opening. A copper layer may be plated in the at least one opening such that a height of the copper layer exceeds a height of the solder resist layer. Further, at least one dielectric layer is deposited above the copper layer, and at least one microvia drilled in the dielectric layer. The at least one microvia enables an electrical connection between at least one of the first side and the second side of the metal panel and a lower surface of the coreless substrate.

Abstract translation: 公开了一种无芯基板及其制造方法。 无芯基板包括能够形成在金属板的第一侧和第二侧上的阻焊层。 阻焊层包括至少一个开口。 铜层可以镀在至少一个开口中，使得铜层的高度超过阻焊层的高度。 此外，至少一个电介质层沉积在铜层之上，并且在介电层中钻出至少一个微孔。 所述至少一个微孔使得能够在金属板的第一侧和第二侧中的至少一个与无芯基板的下表面之间形成电连接。

公开(公告)号：US20120318565A1

公开(公告)日：2012-12-20

申请号：US13595149

申请日：2012-08-27

Applicant: Houssam Jomaa ,  Omar J. Bchir

Inventor： Houssam Jomaa ,  Omar J. Bchir

IPC: H05K1/03

CPC classification number: H05K3/28 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5387 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/3452 ,  H05K2201/0162 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/099 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/05599

Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.

Abstract translation: 微电子器件安装基板包括具有侧壁和上表面的接合焊盘。 电介质第一层设置在安装基板上，并且焊料掩模第二层设置在电介质第一层上。 通过焊接掩模第二层和暴露接合焊盘上表面的部分的电介质第一层设置均匀的凹部。

公开(公告)号：US08067266B2

公开(公告)日：2011-11-29

申请号：US12655089

申请日：2009-12-23

Applicant: Houssam Jomaa

Inventor： Houssam Jomaa

IPC: H01L21/00

CPC classification number: H05K3/4602 ,  B23K1/0016 ,  B23K1/20 ,  B23K2101/40 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/462 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to fabricating substrates for use in microelectronic device packages. In at least one embodiment, two substrate cores may be attached together during build-up layer formation on each substrate core to increase substrate fabrication throughput. The embodiments of the present disclosure may allow the processing of relatively thin substrates.

Abstract translation: 本公开涉及制造用于微电子器件封装的衬底。 在至少一个实施例中，两个衬底芯可以在每个衬底芯上的堆积层形成期间连接在一起，以增加衬底制造生产量。 本公开的实施例可以允许处理相对薄的衬底。

公开(公告)号：US07538021B2

公开(公告)日：2009-05-26

申请号：US11524859

申请日：2006-09-20

Applicant: Houssam Jomaa ,  Omar Bchir

Inventor： Houssam Jomaa ,  Omar Bchir

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/485 ,  H01L23/488

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11009 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K3/3452 ,  H05K2203/0568 ,  H05K2203/0577 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract translation: 在焊料凸点形成期间去除干膜抗蚀剂残留物的技术。 抗蚀剂组件形成在基板上的金属焊盘上。 抗蚀剂组件包括阻焊层（SR）层，多电解质多层（PEMU）和干膜抗蚀剂（DFR）。 在抗蚀剂组件中形成SR开口。 在SR开口上形成焊料凸块。 PEMU被删除。

公开(公告)号：US20080070329A1

公开(公告)日：2008-03-20

申请号：US11524859

申请日：2006-09-20

Applicant: Houssam Jomaa ,  Omar Bchir

Inventor： Houssam Jomaa ,  Omar Bchir

IPC: H01L21/00

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11009 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K3/3452 ,  H05K2203/0568 ,  H05K2203/0577 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract translation: 在焊料凸点形成期间去除干膜抗蚀剂残留物的技术。 抗蚀剂组件形成在基板上的金属焊盘上。 抗蚀剂组件包括阻焊层（SR）层，多电解质多层（PEMU）和干膜抗蚀剂（DFR）。 在抗蚀剂组件中形成SR开口。 在SR开口上形成焊料凸块。 PEMU被删除。

公开(公告)号：US09929097B2

公开(公告)日：2018-03-27

申请号：US14719764

申请日：2015-05-22

Applicant: Ravi Nalla ,  Omar Bchir ,  Houssam Jomaa

Inventor： Ravi Nalla ,  Omar Bchir ,  Houssam Jomaa

IPC: H01L23/532 ,  C08J5/18 ,  H05K3/38 ,  H05K3/46 ,  H01L23/00 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01L23/53238 ,  C08J5/18 ,  C08J2363/00 ,  H01L24/26 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0298 ,  H05K3/181 ,  H05K3/381 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/0773 ,  H05K2203/0796 ,  Y10T156/1052 ,  Y10T428/249921 ,  Y10T428/254 ,  Y10T428/268 ,  H01L2924/00

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

公开(公告)号：US20140248742A1

公开(公告)日：2014-09-04

申请号：US14279165

申请日：2014-05-15

Applicant: Javier Soto Gonzalez ,  Houssam Jomaa

Inventor： Javier Soto Gonzalez ,  Houssam Jomaa

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/95 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/251 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/92244 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.

Abstract translation: 一种装置包括具有接地侧的衬底，该接地侧具有多个接触焊盘和与接地侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。