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1.发明申请公开(公告)号：US20200294582A1
公开(公告)日：2020-09-17
申请号：US16887306
申请日：2020-05-29
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/12 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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2.发明公开公开(公告)号：US20240363165A1
公开(公告)日：2024-10-31
申请号：US18630482
申请日：2024-04-09
IPC分类号： G11C16/04 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/30 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： G11C16/0483 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/30 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.
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公开(公告)号：US12133382B2
公开(公告)日：2024-10-29
申请号：US17678499
申请日：2022-02-23
发明人： Xiang Yin
IPC分类号： H10B41/27 , G11C16/04 , H01L23/522 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.
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公开(公告)号：US12127406B2
公开(公告)日：2024-10-22
申请号：US17577533
申请日：2022-01-18
发明人： Takaaki Iwai , Takashi Inomata , Takayuki Maekura
IPC分类号： H01L25/18 , H01L23/00 , H01L23/535 , H01L25/00 , H01L25/065 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/00
CPC分类号： H10B43/27 , H01L23/535 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/35 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/34 , H10B63/845 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1441 , H01L2924/1444 , H01L2924/14511
摘要： A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
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公开(公告)号：US12125537B2
公开(公告)日：2024-10-22
申请号：US17502398
申请日：2021-10-15
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483
摘要： The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.
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公开(公告)号：US12108597B2
公开(公告)日：2024-10-01
申请号：US17684975
申请日：2022-03-02
发明人： Teruo Okina , Shinsuke Yada , Ryo Yoshimoto
IPC分类号： H10B41/27 , G11C16/04 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H01L2224/06181 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541 , H01L2924/1431 , H01L2924/1451
摘要： A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.
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公开(公告)号：US12106790B2
公开(公告)日：2024-10-01
申请号：US17656306
申请日：2022-03-24
发明人： Alan Kalitsov , Derek Stewart , Ananth Kaushik , Gerardo Bertero
CPC分类号： G11C11/161 , G01R33/093 , G11C11/1673 , G11C11/1675 , H01F10/3286 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
摘要： A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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8.发明授权公开(公告)号：US12105137B2
公开(公告)日：2024-10-01
申请号：US17360573
申请日：2021-06-28
IPC分类号： G01R31/27 , G01R31/317 , G01R31/3181 , G01R31/3183 , G06N3/063
CPC分类号： G01R31/275 , G01R31/31707 , G01R31/31813 , G01R31/31835 , G06N3/063
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
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公开(公告)号：US12096632B2
公开(公告)日：2024-09-17
申请号：US17244311
申请日：2021-04-29
发明人： Koichi Matsuno , Johann Alsmeier
摘要： Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.
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10.发明授权公开(公告)号：US12094943B2
公开(公告)日：2024-09-17
申请号：US17587518
申请日：2022-01-28
发明人： Tomohiro Kubo , Yuki Kasai
IPC分类号： H01L21/00 , H01L21/28 , H01L29/423 , H10B43/27
CPC分类号： H01L29/4234 , H01L29/40117 , H10B43/27
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.
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