公开(公告)号：US12108597B2

公开(公告)日：2024-10-01

申请号：US17684975

申请日：2022-03-02

申请人： SANDISK TECHNOLOGIES LLC

发明人： Teruo Okina ,  Shinsuke Yada ,  Ryo Yoshimoto

IPC分类号： H10B41/27 ,  G11C16/04 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B41/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1451

摘要： A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.