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1427 条记录 (耗时 0.038 秒)

    Memory device and method for forming the same
    83.
    发明授权
    Memory device and method for forming the same 有权
    存储装置及其形成方法

    公开(公告)号：US09401368B2

    公开(公告)日：2016-07-26

    申请号：US14509429

    申请日：2014-10-08

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Zhongshan Hong ,  Yun Yang

    IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    摘要： Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer.

    摘要翻译： 各种实施例提供用于形成它们的存储器件和方法。 提供了一种基板，该基板在其上形成有一个或多个相邻的存储单元。 每个存储单元包括栅极结构，控制栅极层和第一掩模层。 控制栅极层的一部分被去除，以便在平行于衬底的表面的方向上减小控制栅极层的暴露部分的尺寸。 电接触层形成在控制栅极层的暴露侧壁和基板的暴露表面上。 在存储单元的侧壁上形成阻挡层。 在基板上形成导电结构。 该导电结构具有比从栅极结构显着大于控制栅极层的距离，并且阻挡层在导电结构和控制栅极层之间形成隔离层。

    Floating gate NVM with low-moisture-content oxide cap layer
    85.
    发明授权
    Floating gate NVM with low-moisture-content oxide cap layer 有权
    浮动门NVM具有低含水量氧化物盖层

    公开(公告)号：US09379194B2

    公开(公告)日：2016-06-28

    申请号：US14536647

    申请日：2014-11-09

    申请人： Tower Semiconductor Ltd.

    发明人： Micha Gutman ,  Yakov Roizin ,  Allon Parag ,  Vladislav Dayan

    IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L29/04 ,  H01L27/148 ,  H01L27/146 ,  H01L27/115 ,  H01L21/28 ,  H01L21/285

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/285 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14692 ,  H01L27/14698 ,  H01L27/148 ,  H01L29/04 ,  H01L29/66825 ,  H01L29/788

    摘要： A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.

    摘要翻译： 用于非易失性存储器（NVM）的后端金属化结构和包括低含水量氧化物盖层的其它半导体器件，其抑制后端处理期间移动氢原子/离子的产生和迁移。 金属化结构包括在前端形成的多个金属化层，例如多晶硅（浮栅）结构和预金属介电层。 每个金属化层包括由层间电介质（ILD）层（例如，BPSG，USG或FSG）覆盖的图案化金属（例如，铝）结构。 每个盖层使用沉积在下部金属化层中的ILD层上的高密度低含水量氧化物如硅烷氧化物（即，通过硅烷CVD工艺生成的SiO 2）形成，以用作蚀刻停止 用于随后形成的金属层，并且在铝过蚀刻期间将ILD材料与等离子体环境隔离，这显着地减少了氢的产生和迁移，从而减少了浮栅的电荷存储。

    Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices
    87.
    发明授权
    Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices 有权
    包括浮栅晶体管的半导体器件和形成这种半导体器件的方法

    公开(公告)号：US09356157B2

    公开(公告)日：2016-05-31

    申请号：US14223410

    申请日：2014-03-24

    申请人： Micron Technology, Inc.

    发明人： Gurtej S. Sandhu ,  Chandra V. Mouli ,  Di Li

    IPC分类号： H01L29/788 ,  H01L51/52 ,  H01L51/56 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

    摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

    摘要翻译： 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

    SEMICONDUCTOR DEVICE
    89.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160149045A1

    公开(公告)日：2016-05-26

    申请号：US14941930

    申请日：2015-11-16

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI ,  Kazuki TANEMURA

    IPC分类号： H01L29/786 ,  H01L29/788

    CPC分类号： H01L29/7869 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/14612 ,  H01L29/1083 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881

    摘要： A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.

    摘要翻译： 半导体器件包括第一导体，第二导​​体，第一绝缘体，第二绝缘体，第三绝缘体，半导体和电子陷阱层。 半导体包括沟道形成区域。 电子捕获层与通道形成区域重叠，其间插入第二绝缘体。 第一导体与沟道形成区重叠，其间插入第一绝缘体。 第二导体与电子陷阱层重叠，其间插入第三绝缘体。 第二导体不与沟道形成区重叠。