公开(公告)号：US20160133713A1

公开(公告)日：2016-05-12

申请号：US14536647

申请日：2014-11-09

Applicant: Tower Semiconductor Ltd.

Inventor： Micha Gutman ,  Yakov Roizin ,  Allon Parag ,  Vladislav Dayan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/04 ,  H01L21/285 ,  H01L27/146 ,  H01L27/115 ,  H01L21/28 ,  H01L29/788 ,  H01L27/148

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/285 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14692 ,  H01L27/14698 ,  H01L27/148 ,  H01L29/04 ,  H01L29/66825 ,  H01L29/788

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.

Abstract translation: 用于非易失性存储器（NVM）的后端金属化结构和包括低含水量氧化物盖层的其它半导体器件，其抑制后端处理期间移动氢原子/离子的产生和迁移。 金属化结构包括在前端形成的多个金属化层，例如多晶硅（浮栅）结构和预金属介电层。 每个金属化层包括由层间电介质（ILD）层（例如，BPSG，USG或FSG）覆盖的图案化金属（例如，铝）结构。 每个盖层使用沉积在下部金属化层中的ILD层上的高密度低含水量氧化物如硅烷氧化物（即，通过硅烷CVD工艺生成的SiO 2）形成，以用作蚀刻停止 用于随后形成的金属层，并且在铝过蚀刻期间将ILD材料与等离子体环境隔离，这显着地减少了氢的产生和迁移，从而减少了浮栅的电荷存储。

公开(公告)号：US11353597B2

公开(公告)日：2022-06-07

申请号：US16861652

申请日：2020-04-29

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan

IPC: G01T1/02 ,  H01L27/146 ,  H01L31/119 ,  H01L31/0216

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

公开(公告)号：US11644580B2

公开(公告)日：2023-05-09

申请号：US17721012

申请日：2022-04-14

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan

IPC: G01T1/02 ,  H01L27/146 ,  H01L31/119 ,  H01L31/0216

CPC classification number: G01T1/026 ,  H01L27/14623 ,  H01L27/14659 ,  H01L31/02164 ,  H01L31/119

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

公开(公告)号：US20220244410A1

公开(公告)日：2022-08-04

申请号：US17721012

申请日：2022-04-14

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan

IPC: G01T1/02 ,  H01L27/146

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

公开(公告)号：US20150162369A1

公开(公告)日：2015-06-11

申请号：US14101282

申请日：2013-12-09

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan ,  Micha Gutman

IPC: H01L27/146

CPC classification number: H01L27/14659

Abstract: Solid state radiation sensors include a floating gate (FG) structure having a large control capacitor region disposed on thick dielectric portion over a control gate (CG) implemented by an isolated P-well region, and a tunneling capacitor region disposed on thin gate oxide dielectric over another tunneling gate (TG) isolated P-well region. Opposite voltages (e.g., +5V/−5V) are respectively applied to the CG and TG P-well regions to charge the FG structure by Fowler-Nordheim tunneling. During exposure, radiation striking the sensor discharges the FG structure by generating electron-hole pairs in the dielectric portion separating the CG P-well region and the control capacitor region. After exposure, the total ionizing dose (TID) is calculated, e.g., by measuring the threshold voltage shift of a CMOS readout inverter controlled by the residual charge stored on the FG structure. Sensor performance is enhanced by metal plates, utilizing two control capacitors, or modifying the FG electrode layout.

Abstract translation: 固态辐射传感器包括浮置栅极（FG）结构，其具有设置在由隔离的P阱区域实现的控制栅极（CG）上的厚介电部分上的大的控制电容器区域，以及设置在薄栅极氧化物电介质上的隧穿电容器区域 在另一个隧道门（TG）隔离的P阱区域。 分别将相对电压（例如+ 5V / -5V）施加到CG和TG P阱区域，以通过Fowler-Nordheim隧道对FG结构充电。 在曝光期间，撞击传感器的辐射通过在分离CG P阱区域和控制电容器区域的电介质部分中产生电子 - 空穴对来排出FG结构。 曝光后，计算总电离剂量（TID），例如通过测量由FG结构上存储的剩余电荷控制的CMOS读出逆变器的阈值电压偏移。 通过金属板，利用两个控制电容器或修改FG电极布局来增强传感器性能。

公开(公告)号：US20210341632A1

公开(公告)日：2021-11-04

申请号：US16861652

申请日：2020-04-29

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan

IPC: G01T1/02 ,  H01L27/146

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

公开(公告)号：US09379194B2

公开(公告)日：2016-06-28

申请号：US14536647

申请日：2014-11-09

Applicant: Tower Semiconductor Ltd.

Inventor： Micha Gutman ,  Yakov Roizin ,  Allon Parag ,  Vladislav Dayan

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L29/04 ,  H01L27/148 ,  H01L27/146 ,  H01L27/115 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/285 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14692 ,  H01L27/14698 ,  H01L27/148 ,  H01L29/04 ,  H01L29/66825 ,  H01L29/788

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.

Abstract translation: 用于非易失性存储器（NVM）的后端金属化结构和包括低含水量氧化物盖层的其它半导体器件，其抑制后端处理期间移动氢原子/离子的产生和迁移。 金属化结构包括在前端形成的多个金属化层，例如多晶硅（浮栅）结构和预金属介电层。 每个金属化层包括由层间电介质（ILD）层（例如，BPSG，USG或FSG）覆盖的图案化金属（例如，铝）结构。 每个盖层使用沉积在下部金属化层中的ILD层上的高密度低含水量氧化物如硅烷氧化物（即，通过硅烷CVD工艺生成的SiO 2）形成，以用作蚀刻停止 用于随后形成的金属层，并且在铝过蚀刻期间将ILD材料与等离子体环境隔离，这显着地减少了氢的产生和迁移，从而减少了浮栅的电荷存储。

公开(公告)号：US09082867B2

公开(公告)日：2015-07-14

申请号：US13756481

申请日：2013-01-31

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan ,  Micha Gutman

IPC: H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/66833

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract translation: 用于CMOS IC的具有成本效益的SONOS（CEONOS）非易失性存储器（NVM）单元，其中CEONOS NVM单元需要两个或三个附加掩模，但是使用用于形成的相同的标准CMOS流程 NMOS晶体管。 该单元类似于NMOS单元，但是包括替代标准NMOS栅极氧化物并用于存储NVM数据的氧化物 - 氮化物 - 氧化物（ONO）层。 这些电池采用特殊的源极/漏极工程，包括袋式注入和轻掺杂漏极扩展，这有助于使用低电压（例如5V）对CEONOS NVM单元进行编程/擦除。 使用相应的NMOS工艺形成多晶硅栅极，源极/漏极接触和金属化。 CEONOS NVM单元以空间有效的X阵列图案排列，使得每组四个单元共享漏极扩散和三个位线。 编程涉及标准CHE注入或脉冲搅拌界面基板热电子注入（PAISHEI）。

公开(公告)号：US20140209994A1

公开(公告)日：2014-07-31

申请号：US13756481

申请日：2013-01-31

Applicant: TOWER SEMICONDUCTOR LTD.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan ,  Micha Gutman

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/66833

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract translation: 用于CMOS IC的具有成本效益的SONOS（CEONOS）非易失性存储器（NVM）单元，其中CEONOS NVM单元需要两个或三个附加掩模，但是基本上使用用于形成的相同的标准CMOS流程 NMOS晶体管。 该单元类似于NMOS单元，但是包括替代标准NMOS栅极氧化物并用于存储NVM数据的氧化物 - 氮化物 - 氧化物（ONO）层。 这些电池采用特殊的源极/漏极工程，包括袋式注入和轻掺杂漏极扩展，这有助于使用低电压（例如5V）对CEONOS NVM单元进行编程/擦除。 使用相应的NMOS工艺形成多晶硅栅极，源极/漏极接触和金属化。 CEONOS NVM单元以空间有效的X阵列图案排列，使得每组四个单元共享漏极扩散和三个位线。 编程涉及标准CHE注入或脉冲搅拌界面基板热电子注入（PAISHEI）。