公开(公告)号：US08653637B2

公开(公告)日：2014-02-18

申请号：US12700884

申请日：2010-02-05

申请人： Kyung-man Kim ,  In-sang Song

发明人： Kyung-man Kim ,  In-sang Song

IPC分类号： H01L25/11

CPC分类号： H01L23/49575 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip. The semiconductor device also includes a second semiconductor package stacked on the first semiconductor package. The second semiconductor package has at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip. At least one signal connection member is disposed in the first sealing member of the first semiconductor package. The at least one signal connection member electrically connects the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.

摘要翻译： 半导体器件包括具有至少一个第一半导体芯片的第一半导体封装和覆盖该至少一个第一半导体芯片的第一密封构件。 半导体器件还包括堆叠在第一半导体封装上的第二半导体封装。 第二半导体封装具有至少一个第二半导体芯片，电连接到至少一个第二半导体芯片的引线以及覆盖该至少一个第二半导体芯片的第二密封构件。 至少一个信号连接构件设置在第一半导体封装的第一密封构件中。 所述至少一个信号连接构件将所述至少一个第一半导体芯片与所述至少一个第二半导体芯片的引线电连接。

公开(公告)号：US08643153B2

公开(公告)日：2014-02-04

申请号：US13461801

申请日：2012-05-02

申请人： Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

发明人： Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L23/49555 ,  H01L21/4842 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

摘要翻译： 一种用于组装半导体器件的方法包括提供具有天然平面的引线框架和具有天然引线间距的多个引线。 该过程包括修剪和形成多个引线的第一子集以提供第一行引线。 该过程包括修剪和形成多个引线的第二子集以提供第二排引线。 引线的至少一个子集以相对于天平平面的钝角形成，使得与引线的第一或第二子集相关联的引线间距大于原始引线间距。

公开(公告)号：US20140027891A1

公开(公告)日：2014-01-30

申请号：US14110131

申请日：2012-04-03

申请人： Akihiro Kimura ,  Takeshi Sunaga ,  Shouji Yasunaga ,  Akihiro Koga

发明人： Akihiro Kimura ,  Takeshi Sunaga ,  Shouji Yasunaga ,  Akihiro Koga

IPC分类号： H01L21/48 ,  H01L23/495

CPC分类号： H01L23/49568 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed

摘要翻译： 一种方法包括以下步骤：制备包括多个管芯焊盘的引线框架，并制备多个半导体芯片; 将每个所述半导体芯片设置在所述芯片焊盘的相应一个上; 形成密封树脂以覆盖芯片焊盘和半导体芯片; 并且通过在形成密封树脂之后通过作为粘合剂层的树脂片将散热板压靠在模片垫上而将散热板附接到模片垫

公开(公告)号：US20130313715A1

公开(公告)日：2013-11-28

申请号：US13875794

申请日：2013-05-02

申请人： Control Techniques Limited

发明人： Charles Anthony Cachia

IPC分类号： H01L23/00

CPC分类号： H01L24/45 ,  H01L23/49555 ,  H01L23/49562 ,  H01L2224/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/43 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An electronic component including one or more legs for attachment to a circuit board, wherein at least one of said legs includes a spring-acting kink, arranged so as to offers resilience to relative displacement between the end of said leg and the body of said component. The kink may be substantially S-shaped, Z-shaped, U-shaped, wave-shaped or coil-shaped.

摘要翻译： 一种电子部件，包括用于连接到电路板的一个或多个腿部，其中所述腿部中的至少一个包括弹性作用扭结部，其布置成提供弹性，以提供所述腿部的端部和所述部件的主体之间的相对位移 。 扭结可以是大致S形，Z形，U形，波形或线圈形。

公开(公告)号：US20130264696A1

公开(公告)日：2013-10-10

申请号：US13906771

申请日：2013-05-31

申请人： Renesas Eastern Japan Semiconductor, Inc. ,  Renesas Electronics Corporation

发明人： Ryoichi KAJIWARA ,  Masahiro KOIZUMI ,  Toshiaki MORITA ,  Kazuya TAKAHASHI ,  Munehisa KISHIMOTO ,  Shigeru ISHII ,  Toshinori HIRASHIMA ,  Yasushi TAKAHASHI ,  Toshiyuki HATA ,  Hiroshi SATO ,  Keiichi OOKAWA

IPC分类号： H01L23/495

CPC分类号： H01L23/49555 ,  H01L21/4814 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16245 ,  H01L2224/29011 ,  H01L2224/29015 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/73253 ,  H01L2224/75251 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83191 ,  H01L2224/83825 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K3/3426 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2224/29139 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2924/00012

摘要： A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

摘要翻译： 一种半导体器件，其特征在于包括MOSFET的半导体芯片，具有第一主表面和第二主表面，第一主表面上的源极电极焊盘和栅电极焊盘，第二主表面上的漏电极，源极 外部端子和栅极外部端子，每个具有分别电连接到芯片的源电极焊盘和栅电极焊盘的第一主表面和具有第一主表面和第二相对主表面的漏极外部端子，并且是 电连接到芯片的第二主表面，源极，栅极和漏极外部端子中的每一个具有第二主表面在同一平面中，并且在外部端子的平面图中，栅极外部端子具有位于 在至少一个方向上在源极和漏极外部端子之间。

公开(公告)号：US20130256852A1

公开(公告)日：2013-10-03

申请号：US13431758

申请日：2012-03-27

申请人： Michael Todd Wyant ,  Patricia Sabran Conde ,  Vikas Gupta ,  Rajiv Dunne ,  Emerson Mamaril Enipin

发明人： Michael Todd Wyant ,  Patricia Sabran Conde ,  Vikas Gupta ,  Rajiv Dunne ,  Emerson Mamaril Enipin

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L21/50

CPC分类号： H01L23/49524 ,  H01L23/3107 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/40499 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84136 ,  H01L2224/84801 ,  H01L2224/84986 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

摘要翻译： 一种制造具有至少引线框架的堆叠半导体封装的方法，安装在引线框架上方并焊接到引线框架上的第一管芯和安装在上方并焊接到第一管芯的第一夹具。 该方法包括将引线框架，第一模具和第一夹具定位成垂直堆叠的关系，并且非锁定地将第一夹子与引线框架横向不相关的关系锁定。 还公开了堆叠半导体封装和制造堆叠半导体封装中制造的中间产品。

公开(公告)号：US20130163211A1

公开(公告)日：2013-06-27

申请号：US13771431

申请日：2013-02-20

申请人： ROHM CO., LTD.

发明人： Kenichi YOSHIMOCHI

IPC分类号： H05K7/14

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49805 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L29/78 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K7/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

公开(公告)号：US08395251B2

公开(公告)日：2013-03-12

申请号：US11382983

申请日：2006-05-12

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC分类号： H01L23/043

CPC分类号： H01L23/49555 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.

摘要翻译： 提供集成电路封装到封装堆叠系统，包括提供第一集成电路封装，具有构造的引线框架，提供具有所配置的引线框架的第二集成电路封装，以及通过电连接所配置的引线框，形成集成电路封装对 第一集成电路封装到第二集成电路封装的配置的引线框架。

公开(公告)号：US20120068317A1

公开(公告)日：2012-03-22

申请号：US12883556

申请日：2010-09-16

申请人： Belgacem Haba ,  Brian Marcucci

发明人： Belgacem Haba ,  Brian Marcucci

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/89 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

摘要翻译： 示例性实施例的半导体器件包括管芯，引线框架，其包括多个引线，其具有布置在引线平面中并且电连接到管芯的实质部分。 最优选地，封装包括布置在邻近引线框架并且基本上平行于引线平面的平面中的一个导电元件的至少大部分，导电元件电容耦合到引线，使得导电元件和至少一个 引线协调地限定受控阻抗传导路径，以及密封剂，其封装引线和导电元件。 引线和理想的导电元件具有不被密封剂覆盖的各自的连接区域。

公开(公告)号：US20110298020A1

公开(公告)日：2011-12-08

申请号：US13189883

申请日：2011-07-25

申请人： Ryoichi KAJIWARA ,  Masahiro Koizumi ,  Toshiaki Morita ,  Kazuya Takahashi ,  Munehisa Kishimoto ,  Shigeru Ishii ,  Toshinori Hirashima ,  Yasushi Takahashi ,  Toshiyuki Hata ,  Hiroshi Sato ,  Keiichi Ookawa

发明人： Ryoichi KAJIWARA ,  Masahiro Koizumi ,  Toshiaki Morita ,  Kazuya Takahashi ,  Munehisa Kishimoto ,  Shigeru Ishii ,  Toshinori Hirashima ,  Yasushi Takahashi ,  Toshiyuki Hata ,  Hiroshi Sato ,  Keiichi Ookawa

IPC分类号： H01L29/772

CPC分类号： H01L23/49555 ,  H01L21/4814 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16245 ,  H01L2224/29011 ,  H01L2224/29015 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/73253 ,  H01L2224/75251 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83191 ,  H01L2224/83825 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K3/3426 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2224/29139 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2924/00012

摘要： A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

摘要翻译： 一种半导体器件，其中第一金属部件经由包含第一贵金属的第一金属体接合到半导体元件的第一电极，并且第二金属部件经由包含第二贵金属的第二金属体接合到第二电极 金属。