公开(公告)号：US09252199B2

公开(公告)日：2016-02-02

申请号：US14203474

申请日：2014-03-10

Applicant: Realtek Semiconductor Corp.

Inventor： Ta-Hsun Yeh

IPC: H01L49/02 ,  H01L21/768 ,  H01L29/16 ,  H01L23/522 ,  H01L23/64 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/645 ,  H01L25/0657 ,  H01L2224/81 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06572

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.

Abstract translation: 本发明提供集成电感器和集成电感器制造方法。 集成电感器包括：半导体衬底，多个深沟槽和电感器。 深沟槽形成在半导体衬底中并且以特定图案布置，并且深沟槽用金属材料填充以形成图案化接地屏蔽（PGS）。 电感器形成在半导体衬底之上。 集成电感器制造方法包括：形成半导体衬底; 在所述半导体衬底中形成多个深沟槽并以特定图案布置所述深沟槽; 用金属材料填充深沟槽以形成图案化接地屏蔽（PGS）; 以及在半导体衬底上形成电感器。

公开(公告)号：US20160013155A1

公开(公告)日：2016-01-14

申请号：US14328127

申请日：2014-07-10

Applicant: Apple Inc.

Inventor： Chih-Ming Chung

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/552 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4889 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/552 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81

Abstract: In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include a first package, a second package, and a shield. The first package may include a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface substantially opposite the third surface, and a second die. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The shield may be applied to the fourth surface of the semiconductor device package assembly. In some embodiments, the shield may transfer, during use, heat from the first die.

Abstract translation: 在一些实施例中，半导体器件封装可以包括在封装组件上的半导体器件封装。 封装组件上的封装可以包括第一封装，第二封装和屏蔽。 第一封装可以包括第一表面，基本上与第一表面相对的第二表面，第一管芯和耦合到第一表面的第一组电导体，并且被配置为电连接封装组件上的封装。 第二包装可以包括基本上与第三表面相对的第三表面和第四表面，以及第二管芯。 第三表面可以联接到第二表面。 第一封装可以电耦合到第二封装。 屏蔽可以施加到半导体器件封装组件的第四表面。 在一些实施例中，屏蔽件可以在使用期间传递来自第一管芯的热量。

公开(公告)号：US09224699B2

公开(公告)日：2015-12-29

申请号：US14490105

申请日：2014-09-18

Applicant: Jae-Gwon Jang ,  Jin-Woo Park ,  Jong-Ho Lee

Inventor： Jae-Gwon Jang ,  Jin-Woo Park ,  Jong-Ho Lee

IPC: H01L23/552 ,  H01L29/82 ,  H01L21/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/86 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48 ,  H01L2224/48228 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/48227

Abstract: A method of manufacturing a semiconductor package having a magnetic shield function is provided. The method includes forming cracks in a lattice structure on an active surface in which electrode terminals are formed; grinding a back surface of a wafer facing the active surface, bonding a tape on the active surface of the wafer, expanding the tape such that the wafer on the tape is divided as semiconductor chips, forming a shield layer on surfaces of the semiconductor chips and the tape, cutting the shield layer between the semiconductor chips and individualizing as each of the semiconductor chips which has a first shield pattern formed on back surface and sides, bonding the semiconductor chips on a substrate, and forming a second shield pattern on each of the active surfaces of the semiconductor chips, wherein the semiconductor chips and the substrate are physically and electrically connected by a bonding wire.

Abstract translation: 提供一种制造具有磁屏蔽功能的半导体封装的方法。 该方法包括在其中形成电极端子的有源表面上形成栅格结构中的裂纹; 研磨面向活性表面的晶片的背面，将胶带粘合在晶片的有效表面上，使胶带膨胀，使得胶带上的晶片被划分为半导体芯片，在半导体芯片的表面上形成屏蔽层， 在所述半导体芯片之间切割所述屏蔽层，并且将每个所述半导体芯片分别形成在所述半导体芯片的背面和侧面上形成第一屏蔽图案并且将所述半导体芯片接合在基板上，并在所述半导体芯片的每一个上形成第二屏蔽图案 半导体芯片的有源表面，其中半导体芯片和基板通过接合线物理和电连接。

公开(公告)号：US09153543B1

公开(公告)日：2015-10-06

申请号：US13356330

申请日：2012-01-23

Applicant: Marc Alan Mangrum ,  Anthony Panczak

Inventor： Marc Alan Mangrum ,  Anthony Panczak

IPC: H01L23/60 ,  H01L23/06

CPC classification number: H01L23/60 ,  H01L23/04 ,  H01L23/06 ,  H01L23/10 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4909 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In one embodiment a semiconductor package includes a metal lid configured as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to a metalized area located on the surface of the active circuitry, or to an additional metalized die. Appropriate interconnect methods between the lid and the metalized die or metalized area include, but are not restricted to, wire bonding, bumps, tabs, or similar techniques.

Abstract translation: 在一个实施例中，半导体封装包括配置为屏蔽的金属盖，其有效地围绕有源电路，并且因此形成一种法拉第屏蔽。 盖子电耦合到位于有源电路表面上的金属化区域，或耦合到另外的金属化管芯。 盖和金属化模具或金属化区域之间的适当的互连方法包括但不限于引线接合，凸块，突片或类似技术。

公开(公告)号：US20150223322A1

公开(公告)日：2015-08-06

申请号：US14607695

申请日：2015-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/552 ,  H05K7/02 ,  H01L23/12

CPC classification number: H05K1/0237 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/06 ,  H01L24/32 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37624 ,  H01L2224/37647 ,  H01L2224/45014 ,  H01L2224/45032 ,  H01L2224/45099 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01034 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19107 ,  H05K7/02 ,  H01L2224/84

Abstract: A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.

Abstract translation: 封装的器件具有与支撑体结合的半导体材料的裸片。 电磁屏蔽结构围绕裸片并且由延伸到支撑体中的导电材料的格栅结构和耦合在一起的电磁屏蔽形成。 包装质量嵌入模具和电磁屏蔽。 电磁屏蔽由多个金属带部分形成，该金属带部分覆盖在管芯上并嵌入包装物质中。 每个金属带部分的厚度与宽度之比约为1:2至约1:50。

公开(公告)号：US20150214155A1

公开(公告)日：2015-07-30

申请号：US14677376

申请日：2015-04-02

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2023/4056 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

公开(公告)号：US20150194364A1

公开(公告)日：2015-07-09

申请号：US14151156

申请日：2014-01-09

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/36

CPC classification number: H01L23/5286 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2023/4056 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

Abstract translation: 用于三维管芯堆叠的封装，用于制造用于三维管芯堆叠的封装的方法，以及用于在用于三维管芯堆叠的封装中分配电力的方法。 该封装可以包括第一盖子，第二盖子，位于第​​一盖子和第二盖子之间的模具叠层，第一盖子和模具叠层的第一模具之间的第一热界面材料层，以及第二热界面材料 第二盖和模具叠层的第二模具之间的层。 第二热界面材料层由具有高导电性和高导热性的热界面材料构成。

公开(公告)号：US09048127B2

公开(公告)日：2015-06-02

申请号：US14035979

申请日：2013-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Sa-Lly Liu ,  Fu-Lung Hsueh

IPC: H01L27/08 ,  H01L49/02 ,  H01L23/538 ,  H01L23/58 ,  H01L27/06

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US20150115402A1

公开(公告)日：2015-04-30

申请号：US14062924

申请日：2013-10-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Tsung YEN ,  Cheng-Wei LUO

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0694 ,  H01L2223/6622 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.

Abstract translation: 一种感性电容结构，包括第一衬底，第一衬底上的第一导电线，第一衬底上的第一屏蔽层和第一衬底上的第二衬底。

公开(公告)号：US08981579B2

公开(公告)日：2015-03-17

申请号：US14306947

申请日：2014-06-17

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Ellis Chau ,  Wael Zohni ,  Philip Damberg ,  Richard Dewitt Crisp

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/64 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/43

Abstract: A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.

Abstract translation: 公开了能够实现用于凸起的导电元件的期望阻抗的微电子组件。 微电子组件可以包括互连元件，表面导电元件，微电子器件，多个凸起的导电元件和接合元件。 微电子器件可以覆盖在电介质元件和附接到前表面的至少一个表面导电元件。 多个凸起的导电元件可以将元件触点与元件触点连接。 升高的导电元件可以具有在第一高度之上并且至少大致平行于至少一个表面导电元件延伸的基本部分，使得可以为凸起的导电元件实现期望的阻抗。 键合元件可以将至少一个表面导电元件与可连接到参考电位源的至少一个参考触点电连接。