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公开(公告)号：US11417590B2
公开(公告)日：2022-08-16
申请号：US17108270
申请日：2020-12-01
Applicant: STMicroelectronics S.r.l.
Inventor： Federico Giovanni Ziglioli , Alberto Pintus , Pierangelo Magni
IPC: H01L23/495 , H01L21/48 , H01L21/56
Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
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公开(公告)号：US10707153B2
公开(公告)日：2020-07-07
申请号：US15365529
申请日：2016-11-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/495 , H01L21/48 , H01L23/00 , H01L23/31 , H01L25/065
Abstract: A semiconductor device includes: one or more semiconductor dice, a die pad supporting the semiconductor die or dice, a package molded onto the semiconductor die or dice supported by said die pad, wherein the die pad is exposed at the surface of the package, and the exposed die pad with an etched pattern therein to form at least one electrical contact land in the die pad.
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3.发明授权公开(公告)号：US10153229B2
公开(公告)日：2018-12-11
申请号：US15860557
申请日：2018-01-02
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/495 , H01L23/00 , H01L21/66
Abstract: A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding pads, a lead frame for the semiconductor die, a wire bonding layout including electrically conductive wires coupling bonding pads of the semiconductor die with leads in the lead frame. One or more bonding pads of the semiconductor die is/are coupled to a respective lead in the lead frame via a plurality of wires with a plurality of mutually insulated testing lands in the respective lead, so that the plurality of wires are coupled to respective testing lands. The electrical connection between such a bonding pad and the respective lead may be tested by testing the individual electrical connections between the bonding pad and the plurality of testing lands.
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公开(公告)号：US10121720B2
公开(公告)日：2018-11-06
申请号：US15617561
申请日：2017-06-08
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/373 , H01L23/367 , H01L23/31 , H01L23/552 , H01L23/495 , H01L21/56 , H01L21/3205 , H01L21/288 , H01L21/48 , H01L23/00
Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.
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5.发明申请公开(公告)号：US20180190572A1
公开(公告)日：2018-07-05
申请号：US15860557
申请日：2018-01-02
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/495 , H01L23/00 , H01L21/66
CPC classification number: H01L23/49524 , H01L22/14 , H01L22/20 , H01L22/32 , H01L23/495 , H01L23/49534 , H01L23/49548 , H01L23/49558 , H01L24/49 , H01L2224/0392 , H01L2224/0603 , H01L2224/49052 , H01L2224/49109 , H01L2224/49112 , H01L2224/49173 , H01L2924/00014 , H01L2224/45099
Abstract: A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding pads, a lead frame for the semiconductor die, a wire bonding layout including electrically conductive wires coupling bonding pads of the semiconductor die with leads in the lead frame. One or more bonding pads of the semiconductor die is/are coupled to a respective lead in the lead frame via a plurality of wires with a plurality of mutually insulated testing lands in the respective lead, so that the plurality of wires are coupled to respective testing lands. The electrical connection between such a bonding pad and the respective lead may be tested by testing the individual electrical connections between the bonding pad and the plurality of testing lands.
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Patent Agency Ranking
公开(公告)号：US09887165B2
公开(公告)日：2018-02-06
申请号：US14565934
申请日：2014-12-10
Applicant: STMICROELECTRONICS S.r.l.
CPC classification number: H01L23/562 , G01R31/2872 , H01L21/76224 , H01L22/14 , H01L23/585 , H01L2924/0002 , H01L2924/00
Abstract: An IC may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The IC may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side.
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公开(公告)号：USRE46671E1
公开(公告)日：2018-01-16
申请号：US14069136
申请日：2013-10-31
Applicant: STMicroelectronics S.r.l.
Inventor： Chantal Combi , Benedetto Vigna , Federico Giovanni Ziglioli , Lorenzo Baldo , Manuela Magugliani , Ernesto Lasalandra , Caterina Riva
CPC classification number: B81B7/0061 , B81B7/02 , B81B2201/0235 , B81B2201/0264 , B81C1/0023 , H01L2224/48091 , H01L2224/73265 , H01L2924/1461 , H01L2924/3025 , H04R1/04 , H04R19/005 , H01L2924/00014 , H01L2924/00
Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.
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公开(公告)号：US09761511B2
公开(公告)日：2017-09-12
申请号：US14980546
申请日：2015-12-28
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00
CPC classification number: H01L23/49541 , H01L21/4825 , H01L21/4842 , H01L21/568 , H01L23/4952 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/45015 , H01L2224/45144 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
Abstract: An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing.
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9.发明授权公开(公告)号：US09096421B2
公开(公告)日：2015-08-04
申请号：US13922577
申请日：2013-06-20
Applicant: STMicroelectronics S.r.l.
Inventor： Federico Giovanni Ziglioli
CPC classification number: B81B7/007 , B81B7/008 , B81C1/0023 , B81C1/00301 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/10158 , H01L2924/15192 , H01L2924/181 , H01L2924/18161 , H01L2924/00014 , H01L2924/00012
Abstract: An assembly of a MEMS integrated device envisages: a package having a base substrate with a main surface in a horizontal plane, and a coating set on the base substrate; a first body including semiconductor material and integrating a micromechanical structure, housed within the package on the base substrate; at least one second body including semiconductor material and integrating at least one electronic component, designed to be functionally coupled to the micromechanical structure, the first body and the second body being arranged within the package stacked in a vertical direction transverse to the horizontal plane. In particular, at least one between the first body and the base substrate defines a first recess, in which the second body is housed, at least in part.
Abstract translation: MEMS集成装置的组件设想：具有在水平面中具有主表面的基底基底和在基底基底上的涂层的封装; 包含半导体材料并将容纳在所述封装内的微机械结构集成在所述基底基板上的第一体; 包括半导体材料的至少一个第二主体并且集成至少一个电子部件，被设计成功能上耦合到微机械结构，第一主体和第二主体被布置在横向于水平面的垂直方向上堆叠的封装内。 特别地，第一主体和基底基板之间的至少一个至少部分地限定了容纳第二主体的第一凹部。
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公开(公告)号：US11552024B2
公开(公告)日：2023-01-10
申请号：US16990748
申请日：2020-08-11
Applicant: STMicroelectronics S.r.l.
Inventor： Federico Giovanni Ziglioli , Alberto Pintus , Michele Derai , Pierangelo Magni
Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.
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