公开(公告)号：US20170352660A1

公开(公告)日：2017-12-07

申请号：US15684442

申请日：2017-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Fu-Huan Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Han-Min Tsai ,  Hong-Lin Chu

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/167 ,  H03D7/14 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785 ,  H03D7/1441 ,  H03D7/1458

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

公开(公告)号：US20150214892A1

公开(公告)日：2015-07-30

申请号：US14165765

申请日：2014-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Chewn-Pu Jou

IPC: H03B5/12 ,  H03L7/099 ,  H01L27/08 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

CPC classification number: H03B5/1275 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0886 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0995

Abstract: The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor.

Abstract translation: 本公开涉及具有一个或多个控制元件的FinFET变容二极管电路，其控制FinFET MOS变容二极管的电容和电压之间的关系，而不引入对用于制造FinFET MOS变容二极管的工艺参数的改变。 在一些实施例中，FinFET变容二极管电路具有FinFET MOS可变电抗器，其第一端子连接到FinFET MOS可变电抗器的栅极端子，第二端子连接到FinFET MOS可变容量管的连接的源极和漏极端子。 一个或多个控制元件连接到FinFET MOS变容二极管的第一或第二端子，并改变FinFET MOS变容二极管的一个或多个工作特性。 使用控制元件改变FinFET MOS变容二极管的工作特性，允许调整特性，而不会改变FinFET MOS变容二极管制造过程中使用的工艺参数。

公开(公告)号：US11079428B2

公开(公告)日：2021-08-03

申请号：US16845515

申请日：2020-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/28

Abstract: A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.

公开(公告)号：US09929760B2

公开(公告)日：2018-03-27

申请号：US15098784

申请日：2016-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Lin Chu ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

IPC: H04B1/18 ,  H04B1/10 ,  H03F3/193 ,  H03H19/00 ,  H03F3/45

CPC classification number: H04B1/1036 ,  H03F1/565 ,  H03F3/193 ,  H03F3/3022 ,  H03F3/45071 ,  H03F2200/165 ,  H03F2200/171 ,  H03F2200/213 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/30031 ,  H03F2203/45288 ,  H03H19/004

Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

公开(公告)号：US09761584B2

公开(公告)日：2017-09-12

申请号：US14732661

申请日：2015-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Fu-Huan Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Han-Min Tsai ,  Hong-Lin Chu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/167 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H03D7/14

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42376 ,  H03D7/1441 ,  H03D7/1458

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

公开(公告)号：US10529711B2

公开(公告)日：2020-01-07

申请号：US15684442

申请日：2017-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Fu-Huan Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Han-Min Tsai ,  Hong-Lin Chu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/167 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H03D7/14 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

公开(公告)号：US09991721B2

公开(公告)日：2018-06-05

申请号：US14918615

申请日：2015-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-De Jin ,  Fan-Ming Kuo ,  Huan-Neng Chen ,  Ming-Hsien Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

IPC: H02J5/00 ,  H01F5/00 ,  H02J50/12 ,  H01F17/00 ,  H01F38/14 ,  H02J17/00

CPC classification number: H02J5/005 ,  H01F5/00 ,  H01F17/0006 ,  H01F38/14 ,  H01F2017/0086 ,  H02J17/00 ,  H02J50/12

Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.

公开(公告)号：US11063559B2

公开(公告)日：2021-07-13

申请号：US14732670

申请日：2015-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Fu-Huan Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Han-Min Tsai ,  Hong-Lin Chu

IPC: H03D7/14 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

公开(公告)号：US10256783B2

公开(公告)日：2019-04-09

申请号：US15714395

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Lin Chu ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

IPC: H03F3/72 ,  H04B1/04 ,  H03C1/36

Abstract: A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.

公开(公告)号：US09548267B2

公开(公告)日：2017-01-17

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Sa-Lly Liu ,  Fu-Lung Hsueh

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/538 ,  H01L23/58 ,  H01L27/06 ,  H01L27/07 ,  H01L23/48 ,  H03F1/26 ,  H03F3/04 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。