公开(公告)号：US11837505B2

公开(公告)日：2023-12-05

申请号：US17813862

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US11835572B2

公开(公告)日：2023-12-05

申请号：US17223543

申请日：2021-04-06

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: G01R31/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: G01R31/2851 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.

公开(公告)号：US20230386904A1

公开(公告)日：2023-11-30

申请号：US18360617

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L23/485 ,  H01L21/764 ,  H01L29/417

CPC classification number: H01L21/7682 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/76882 ,  H01L23/53295 ,  H01L21/28568 ,  H01L21/31116 ,  H01L23/53209 ,  H01L23/528 ,  H01L21/76843 ,  H01L23/485 ,  H01L21/76897 ,  H01L21/764 ,  H01L21/76883 ,  H01L29/41791 ,  H01L21/823431

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

公开(公告)号：US20230378167A1

公开(公告)日：2023-11-23

申请号：US17844742

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823431

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

公开(公告)号：US20230378157A1

公开(公告)日：2023-11-23

申请号：US18361454

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jack Liu

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/528 ,  H01L21/8234 ,  G06F30/31 ,  G06F117/12

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5286 ,  H01L21/823475 ,  G06F30/31 ,  G06F2117/12

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

公开(公告)号：US20230378056A1

公开(公告)日：2023-11-23

申请号：US18362731

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

Inventor： Chenming HU ,  Shu-Jui CHANG ,  Chen-Han CHOU ,  Yen-Teng HO ,  Chia-Hsing WU ,  Kai-Yu PENG ,  Cheng-Hung SHEN

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/02581 ,  H01L21/823475

Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

公开(公告)号：US11824010B2

公开(公告)日：2023-11-21

申请号：US17682734

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Owen Fay ,  Chan H. Yoo

IPC: H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/823475 ,  H01L23/147 ,  H01L23/5383 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/18 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/2518 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443

Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.

公开(公告)号：US20230369127A1

公开(公告)日：2023-11-16

申请号：US17745578

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tun-Jen CHANG ,  Tung-Heng HSIEH ,  Bao-Ru YOUNG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L27/0886 ,  H01L29/41791 ,  H01L21/823431

Abstract: A method includes forming a fin structure over a substrate, forming a first source/drain feature and a second source/drain feature over the fin structure, forming a dielectric material over the first source/drain feature and the second source/drain feature, patterning the dielectric layer into insulating features, and forming a first contact plug on the first source/drain feature and a second contact plug on the second source/drain feature. The insulating features include a first insulating feature and a second insulating feature on opposite sides of the first source/drain feature, and a third insulating feature and a fourth insulating feature on opposite sides of the second source/drain feature. The first insulating feature is longer than the third insulating feature. The distance between the first and second insulating features is greater than the distance between the third and fourth insulating features.

公开(公告)号：US20230361116A1

公开(公告)日：2023-11-09

申请号：US18224000

申请日：2023-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yuan LU ,  Sai-Hooi YEONG

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/0886 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/165 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/28525 ,  H01L29/4966

Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

公开(公告)号：US20230352526A1

公开(公告)日：2023-11-02

申请号：US18350187

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYUHWAN AHN ,  SUNG SOO KIM ,  CHAEHO NA ,  WOONGSIK NAM ,  DONGHYUN ROH

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823475 ,  H01L21/823412 ,  H01L29/66795 ,  H01L27/0886

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.