公开(公告)号：US09324799B2

公开(公告)日：2016-04-26

申请号：US14480974

申请日：2014-09-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC分类号： H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

摘要： Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

摘要翻译： 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。

公开(公告)号：US09318448B2

公开(公告)日：2016-04-19

申请号：US14401132

申请日：2012-05-30

申请人： Patrice Besse ,  Kamel Abouda ,  Valerie Bernon-Enjalbert ,  Philippe Givelin

发明人： Patrice Besse ,  Kamel Abouda ,  Valerie Bernon-Enjalbert ,  Philippe Givelin

IPC分类号： H01L23/60 ,  H01L27/02 ,  H01L21/761 ,  H01L21/762 ,  H01L27/04 ,  H01L29/74

CPC分类号： H01L23/60 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0262 ,  H01L27/04 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/13034 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component.

摘要翻译： 描述了包括封装和半导体器件的封装半导体器件。 半导体器件包括分别与第一和第二接合线接合到一个或多个GND引脚的第一和第二GND焊盘，用第三接合线接合到第一功能引脚的第一功能焊盘，半导体层 P型导电性，第一半导体元件和第二半导体元件。 第一半导体部件被布置成当瞬态电流被施加到第一功能引脚时，至少一部分瞬态电流从第一P区转移到第一GND焊盘，至少一个 第一PN结。 第二半导体部件包括与第一功能焊盘相关联的第二半导体部件的端子的第二N型区域。 第一GND焊盘与第二P型区域接触。 第二GND焊盘与第三N型区域接触。 第二P型区域的至少一部分配置在第一半导体部件和第二半导体部件之间，第三N型区域的至少一部分配置在第一P型区域的至少一部分之间 和第二半导体部件。

公开(公告)号：US20160104799A1

公开(公告)日：2016-04-14

申请号：US14511715

申请日：2014-10-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi QI ,  Catherine B. LABELLE ,  Xiuyu CAI

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/775

CPC分类号： H01L29/7849 ,  B82Y10/00 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/775

摘要： A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

摘要翻译： 提供具有绝缘隔离的双应变Si和SiGe FinFET器件和双应变纳米线器件及其形成方法。 实施例包括形成在硅衬底上的SiGe SRB，SRB具有第一区域和第二区域; 分别形成在SiGe SRB的第一区域和第二区域上的第一和第二介电隔离层; 形成在第一介电隔离层上的拉伸应变Si翅片; 形成在所述第二介电隔离层上的压缩应变SiGe鳍; 形成在拉伸应变Si翅片的相对侧的第一源极/漏极区域; 形成在压缩应变SiGe翅片的相对侧的第二源极/漏极区域; 形成在第一源/漏区之间的第一RMG; 以及形成在第二源/漏区之间的第二RMG。

公开(公告)号：US20160086843A1

公开(公告)日：2016-03-24

申请号：US14957585

申请日：2015-12-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US09286425B2

公开(公告)日：2016-03-15

申请号：US13747798

申请日：2013-01-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/8238 ,  G06F17/50 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： G06F17/5045 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

公开(公告)号：US20160071932A1

公开(公告)日：2016-03-10

申请号：US14480974

申请日：2014-09-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC分类号： H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/36

CPC分类号： H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

摘要： Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

公开(公告)号：US20160064552A1

公开(公告)日：2016-03-03

申请号：US14808026

申请日：2015-07-24

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： YONG CHENG ,  XIANYONG PU ,  HAIQIANG WANG

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L21/02164 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region.

摘要翻译： LDMOS晶体管包括具有第一掺杂类型的半导体衬底; 形成在所述半导体衬底中的多个第一沟槽; 具有增加的导电路径和第二掺杂类型的波形漂移区，形成在相邻的第一沟槽和由第一沟槽的侧表面和底表面暴露的半导体衬底之间的半导体衬底上; 形成在每个第一沟槽中的第一浅沟槽隔离（STI）结构; 在所述漂移区的一侧的半导体衬底中形成具有所述第一掺杂类型的体区; 形成在身体区域，漂移区域和最接近身体区域的第一STI结构的部分上的栅极结构; 形成在所述身体区域中的源区域; 以及形成在最靠近身体区域的第一STI结构的一侧的漂移区域中的漏极区域。

公开(公告)号：US09276062B2

公开(公告)日：2016-03-01

申请号：US14504149

申请日：2014-10-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/84 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/785

摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

摘要翻译： 一种方法包括形成从半导体衬底的顶表面延伸到半导体衬底中的多个沟槽，其中半导体条形成在多个沟槽之间。 多个沟槽包括比第一沟槽宽的第一沟槽和第二沟槽。 第一介电材料填充在多个沟槽中，其中第一沟槽基本上完全填充，并且第二沟槽被部分填充。 在第一电介质材料上形成第二电介质材料。 第二介电材料填充第二沟槽的上部，并且具有与第一电介质材料的第一收缩率不同的收缩率。 执行平面化以去除多余的第二电介质材料。 第一介电材料和第二介电材料的剩余部分分别在第一和第二沟槽中形成第一和第二STI区。

公开(公告)号：US09269616B2

公开(公告)日：2016-02-23

申请号：US14153848

申请日：2014-01-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Zhuo-Cang Yang ,  Chih-Kuan Chen

IPC分类号： H01L21/70 ,  H01L21/768 ,  H01L29/417 ,  H01L27/12 ,  H01L27/06

CPC分类号： H01L21/76877 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/8605 ,  H01L29/8611

摘要： Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer.

摘要翻译： 提供半导体器件结构的实施例和形成半导体器件结构的方法。 半导体器件结构包括具有顶表面，底表面和侧表面的绝缘层。 半导体器件结构还包括形成在第一绝缘层的底表面上的第一半导体衬底。 半导体器件结构还包括仅在第一半导体衬底上与绝缘层的侧表面相邻形成的导电特征。 此外，半导体器件结构包括形成在绝缘层的顶表面上的第二半导体衬底。 第二半导体衬底包括直接在绝缘层上方形成的器件形成区域，使得器件形成区域的突出区域位于绝缘层的内部。

公开(公告)号：US09257325B2

公开(公告)日：2016-02-09

申请号：US12562849

申请日：2009-09-18

申请人： Andreas Knorr ,  Frank Scott Johnson

发明人： Andreas Knorr ,  Frank Scott Johnson

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

摘要： Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

摘要翻译： 提供了用于形成由体硅晶片形成的翅片结构之间的隔离的半导体结构和方法。 提供具有由其形成的一个或多个翅片结构的体硅晶片。 翅片结构的形成限定了一个或多个翅片结构之间的隔离沟槽。 每个翅片结构都具有垂直侧壁。 使用HDPCVD以大约4:1的比例或更大的比例在隔离沟槽和垂直侧壁上沉积氧化物层。 氧化层被各向同性蚀刻以从隔离沟底部的垂直侧壁和氧化物层的一部分去除氧化物层。 在隔离沟槽的底部上形成基本上均匀的厚的隔离氧化物层，以隔离一个或多个翅片结构，并显着降低翅片高度的可变性。