公开(公告)号：US20150340274A1

公开(公告)日：2015-11-26

申请号：US14286029

申请日：2014-05-23

申请人： GLOBALFOUNDRIES, Inc.

发明人： Errol Todd Ryan ,  Sukwon Hong

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L21/02

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02348 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823431 ,  H01L29/66795

摘要： Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less.

摘要翻译： 提供了集成电路的制造方法。 一种用于制造集成电路的方法包括形成覆盖在衬底上的绝缘层，其中绝缘层形成在沟槽内。 绝缘层注入水，绝缘层在照射下退火。 绝缘层在约800摄氏度或更低的干燥退火温度下退火。

公开(公告)号：US09786607B2

公开(公告)日：2017-10-10

申请号：US15277732

申请日：2016-09-27

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, Jr.

IPC分类号： H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

公开(公告)号：US20170140984A1

公开(公告)日：2017-05-18

申请号：US15420467

申请日：2017-01-31

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

公开(公告)号：US09324799B2

公开(公告)日：2016-04-26

申请号：US14480974

申请日：2014-09-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC分类号： H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

摘要： Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

摘要翻译： 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。

公开(公告)号：US09646884B2

公开(公告)日：2017-05-09

申请号：US14699122

申请日：2015-04-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Sukwon Hong ,  Hoon Kim ,  Min Gyu Sung

IPC分类号： H01L21/8234 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/28

CPC分类号： H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

摘要： The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

公开(公告)号：US20170018459A1

公开(公告)日：2017-01-19

申请号：US15277732

申请日：2016-09-27

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

摘要翻译： 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

公开(公告)号：US10014209B2

公开(公告)日：2018-07-03

申请号：US15630546

申请日：2017-06-22

申请人： GLOBALFOUNDRIES INC.

发明人： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

摘要： At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US09831098B2

公开(公告)日：2017-11-28

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/3105 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

公开(公告)号：US09583442B2

公开(公告)日：2017-02-28

申请号：US14753407

申请日：2015-06-29

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, Jr.

IPC分类号： H01L21/4763 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

摘要翻译： 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

公开(公告)号：US09236308B1

公开(公告)日：2016-01-12

申请号：US14463013

申请日：2014-08-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC分类号： H01L21/8242 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/31116 ,  H01L27/0886 ,  H01L29/66818

摘要： Methods of fabricating fin structures having exposed upper fin portions with a uniform exposure height are disclosed herein. The fabrication methods include providing a substrate with plurality of fins and a dielectric material disposed between and over the plurality of fins, planarizing the dielectric material and the plurality of fins, and uniformly recessing the dielectric material to a pre-selected depth below upper surfaces of the plurality of fins to expose upper fin portions. The exposed upper fin portions, as a result of uniformly recessing the dielectric material, have a uniform exposure height above the recessed dielectric material. A protective film may be provided over the recessed dielectric material and exposed upper fin portions to preserve the uniform exposure height of the upper fin portions. The uniform exposure height of the exposed upper fin portions facilitates subsequent formation of one or more circuit structures above the substrate.

摘要翻译： 本文公开了制造具有暴露的具有均匀曝光高度的上翅片部分的翅片结构的方法。 制造方法包括提供具有多个翅片的基板和设置在多个翅片之间和之上的介电材料，平坦化介电材料和多个翅片，并均匀地将电介质材料凹陷到下表面下方的预选深度 多个翅片以暴露上部翅片部分。 暴露的上部翅片部分，由于均匀地凹陷介电材料，在凹入的电介质材料上方具有均匀的曝光高度。 可以在凹陷的电介质材料和暴露的上部翅片部分上设置保护膜，以保持上部翅片部分的均匀的曝光高度。 暴露的上部翅片部分的均匀曝光高度有助于随后在基底上方形成一个或多个电路结构。