公开(公告)号：US10170367B2

公开(公告)日：2019-01-01

申请号：US15725805

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu Chao Lin ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Wei-Che Hsieh ,  Chun-Hung Lee

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/308 ,  H01L29/66 ,  H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

摘要： In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.

公开(公告)号：US20180151441A1

公开(公告)日：2018-05-31

申请号：US15725805

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu Chao Lin ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Wei-Che Hsieh ,  Chun-Hung Lee

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/308

CPC分类号： H01L21/823431 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

摘要： In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.

公开(公告)号：US20160351692A1

公开(公告)日：2016-12-01

申请号：US15233319

申请日：2016-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tai-Chun Huang ,  Chih-Tang Peng ,  Chia-Wei Chang ,  Ming-Hua Yu ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Tze-Liang Lee

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/306 ,  H01L21/308 ,  H01L21/84 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7856

摘要： An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

摘要翻译： 集成电路器件包括半导体衬底和延伸到半导体衬底中的半导体条。 第一和第二电介质区域位于半导体条的相对侧并与其接触。 第一电介质区域和第二电介质区域中的每一个包括具有半导体条的第一部分电平和低于半导体条的第二部分。 第二部分还包括与半导体条重叠的部分。

公开(公告)号：US08895446B2

公开(公告)日：2014-11-25

申请号：US13769783

申请日：2013-02-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L21/762

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/785

摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

摘要翻译： 一种方法包括形成从半导体衬底的顶表面延伸到半导体衬底中的多个沟槽，其中半导体条形成在多个沟槽之间。 多个沟槽包括比第一沟槽宽的第一沟槽和第二沟槽。 第一介电材料填充在多个沟槽中，其中第一沟槽基本上完全填充，并且第二沟槽被部分填充。 在第一电介质材料上形成第二电介质材料。 第二介电材料填充第二沟槽的上部，并且具有与第一电介质材料的第一收缩率不同的收缩率。 执行平面化以去除多余的第二电介质材料。 第一介电材料和第二介电材料的剩余部分分别在第一和第二沟槽中形成第一和第二STI区。

公开(公告)号：US20140264491A1

公开(公告)日：2014-09-18

申请号：US13866841

申请日：2013-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tai-Chun Huang ,  Chih-Tang Peng ,  Chia-Wei Chang ,  Ming-Hua Yu ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Tze-Liang Lee

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7856

摘要： An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

摘要翻译： 集成电路器件包括半导体衬底和延伸到半导体衬底中的半导体条。 第一和第二电介质区域位于半导体条的相对侧并与其接触。 第一电介质区域和第二电介质区域中的每一个包括具有半导体条的第一部分电平和低于半导体条的第二部分。 第二部分还包括与半导体条重叠的部分。

公开(公告)号：US20140231919A1

公开(公告)日：2014-08-21

申请号：US13769783

申请日：2013-02-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

IPC分类号： H01L21/762 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/785

摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

摘要翻译： 一种方法包括形成从半导体衬底的顶表面延伸到半导体衬底中的多个沟槽，其中半导体条形成在多个沟槽之间。 多个沟槽包括比第一沟槽宽的第一沟槽和第二沟槽。 第一介电材料填充在多个沟槽中，其中第一沟槽基本上完全填充，并且第二沟槽被部分填充。 在第一电介质材料上形成第二电介质材料。 第二介电材料填充第二沟槽的上部，并且具有与第一电介质材料的第一收缩率不同的收缩率。 执行平面化以去除多余的第二电介质材料。 第一介电材料和第二介电材料的剩余部分分别在第一和第二沟槽中形成第一和第二STI区。

公开(公告)号：US20140170319A1

公开(公告)日：2014-06-19

申请号：US13716052

申请日：2012-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Che Hsieh ,  Brian Wang ,  Tze-Liang Lee ,  Yi-Hung Lin ,  Hao-Ming Lien ,  Shiang-Rung Tsai ,  Tai-Chun Huang

IPC分类号： B05B1/14

CPC分类号： C23C16/45578 ,  C23C16/45504 ,  C23C16/45546 ,  C23C16/4584 ,  C23C16/52 ,  C23C16/54 ,  H01L21/00

摘要： An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.

摘要翻译： 提供了分别在一叠晶片上形成薄膜的注射器。 喷射器包括多个孔结构。 每个相邻的两个晶片之间具有晶片间隔，并且每个晶片具有工作表面。 孔结构分别对应于相应的晶片间隔。 工作表面和相应的孔结构之间具有平行的距离。 平行距离大于晶片间距的一半。 还提供了晶片处理装置和分别在晶片叠层上形成薄膜的方法。

公开(公告)号：US08629508B2

公开(公告)日：2014-01-14

申请号：US13711323

申请日：2012-12-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Tang Peng ,  Bing-Hung Chen ,  Tze-Liang Lee ,  Hao-Ming Lien

IPC分类号： H01L21/02

CPC分类号： H01L21/76843 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/02348 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76876 ,  H01L21/76877 ,  H01L29/0649

摘要： A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

摘要翻译： 提供一种用于形成隔离沟槽的系统和方法。 一个实施例包括形成沟槽，然后用电介质衬垫衬套沟槽。 在蚀刻电介质衬垫之前，使用放气过程来去除可能从电介质衬垫的沉积中留下的残余前体材料。 在除气过程之后，可以蚀刻电介质衬垫，并且可以用电介质材料填充沟槽。

公开(公告)号：US10316411B2

公开(公告)日：2019-06-11

申请号：US14665346

申请日：2015-03-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Wei-Che Hsieh ,  Brian Wang ,  Tze-Liang Lee ,  Yi-Hung Lin ,  Hao-Ming Lien ,  Shiang-Rung Tsai ,  Tai-Chun Huang

IPC分类号： C23C16/455 ,  H01L21/00 ,  C23C16/458 ,  C23C16/54 ,  C23C16/52

摘要： An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.

公开(公告)号：US10269937B2

公开(公告)日：2019-04-23

申请号：US15864575

申请日：2018-01-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tai-Chun Huang ,  Chih-Tang Peng ,  Chia-Wei Chang ,  Ming-Hua Yu ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Tze-Liang Lee

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L29/06 ,  H01L21/764 ,  H01L21/84 ,  H01L29/78 ,  H01L29/423

摘要： An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.