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    Techniques for MRAM MTJ top electrode connection
    82.
    发明授权
    Techniques for MRAM MTJ top electrode connection 有权

    公开(公告)号：US09818935B2

    公开(公告)日：2017-11-14

    申请号：US15000289

    申请日：2016-01-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

    IPC: H01L43/12 ,  H01L43/08 ,  H01L43/04 ,  H01L27/22

    CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

    SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI)
    87.
    发明申请
    SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) 有权
    硅胶分离和外延沉积用于低温分离（STI）

    公开(公告)号：US20170062559A1

    公开(公告)日：2017-03-02

    申请号：US15349100

    申请日：2016-11-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

    Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

    Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

    Method to prevent oxide damage and residue contamination for memory device
    90.
    发明授权
    Method to prevent oxide damage and residue contamination for memory device 有权
    防止存储器件氧化物损坏和残留污染的方法

    公开(公告)号：US09536888B2

    公开(公告)日：2017-01-03

    申请号：US14580505

    申请日：2014-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chang-Ming Wu ,  Harry-Hak-Lay Chuang ,  Shih-Chang Liu

    IPC: H01L31/112 ,  H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L27/115 ,  H01L21/28

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

    Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

    Abstract translation: 本公开涉及一种形成集成电路的方法。 在一些实施例中，该方法通过在衬底上图案化第一掩模层来进行，以在存储单元区域处具有第一多个开口，并在边界区域具有第二多个开口。 在所述第一多个开口内形成有第一多个介电体，并且在所述第二多个开口内形成第二多个介电体。 在第一掩蔽层和第一和第二多个电介质体之上形成第二掩模层。 在存储单元区域处去除第一和第二掩模层，并且形成第一导电层以填充第一多个电介质体之间的凹部。 平坦化处理降低了第一导电层的高度，并从边界区域上移除第一导电层。

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