公开(公告)号：US20180240799A1

公开(公告)日：2018-08-23

申请号：US15959832

申请日：2018-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/8258 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

公开(公告)号：US20180225567A1

公开(公告)日：2018-08-09

申请号：US15802669

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen W. Bedell ,  Martin M. Frank ,  Devendra K. Sadana

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  H01L27/06 ,  H01L49/02 ,  H01L29/808

CPC classification number: G06N3/0635 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/08 ,  G06N3/084 ,  H01L28/20 ,  H01L28/40

Abstract: Methods of training a neural network include applying an input signal to an array of weights to generate weighted output signals based on resistances of respective weights in the array of weights. A difference between the weighted output signals and a predetermined expected output is determined. Weights in the array of weights are set by applying a pulse to a controllable resistance element in each weight. The pulse increments or decrements a charge on a junction field effect transistor in the respective controllable resistance element.

公开(公告)号：US20180013070A1

公开(公告)日：2018-01-11

申请号：US15699527

申请日：2017-09-08

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L51/00 ,  H01L51/10 ,  H01L51/05

CPC classification number: H01L51/0049 ,  H01L51/0048 ,  H01L51/0575 ,  H01L51/102 ,  H01L2251/301 ,  H01L2251/303 ,  Y10S977/938

Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.

公开(公告)号：US20180006131A1

公开(公告)日：2018-01-04

申请号：US15198964

申请日：2016-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy M. Cohen ,  Martin M. Frank

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/517 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/7843

Abstract: A transistor device includes a source region, a drain region and a III-V channel material disposed between the source and drain region. A gate dielectric layer is epitaxially grown on the III-V channel material. The gate dielectric layer includes a (X)Se compound, wherein X includes one or more of Zn, Cd and/or Mg. A gate conductor is formed on the gate dielectric layer.

公开(公告)号：US09806265B1

公开(公告)日：2017-10-31

申请号：US15092894

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L51/00 ,  H01L51/10 ,  H01L51/05

CPC classification number: H01L51/0049 ,  H01L51/0048 ,  H01L51/0575 ,  H01L51/102 ,  H01L2251/301 ,  H01L2251/303

Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.

公开(公告)号：US20170309519A1

公开(公告)日：2017-10-26

申请号：US15649182

申请日：2017-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan

IPC: H01L21/8258 ,  H01L29/20 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/51 ,  H01L29/16

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US20170243867A1

公开(公告)日：2017-08-24

申请号：US15051790

申请日：2016-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/8258 ,  H01L27/092

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US20170092501A1

公开(公告)日：2017-03-30

申请号：US14962093

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Martin M. Frank ,  Vijay Narayanan ,  John Rozen

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L29/401 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/32105 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66757 ,  H01L29/66795

Abstract: A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.

公开(公告)号：US09472553B1

公开(公告)日：2016-10-18

申请号：US15093232

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/823842 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium containing semiconductor material. An n-type planar FET is present in the first region of the substrate. A p-type planar FET is present in a second region of the substrate. A gate structure for each of the n-type planar FET and the p-type planar FET includes a metal containing layer including at least one of titanium and aluminum atop a high-k gate dielectric. An effective work function of the gate structure for both the n-type and p-type planar FETs is a less than a mid gap of silicon.

公开(公告)号：US20160133753A1

公开(公告)日：2016-05-12

申请号：US14994821

申请日：2016-01-13

Applicant: International Business Machines Corporation

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Vijay Narayanan

IPC: H01L29/78

CPC classification number: H01L29/78391 ,  H01L21/28088 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684

Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.