公开(公告)号：US20170170323A1

公开(公告)日：2017-06-15

申请号：US15336654

申请日：2016-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/762 ,  H01L21/76202 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

公开(公告)号：US09634006B2

公开(公告)日：2017-04-25

申请号：US14193849

申请日：2014-02-28

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Sameer H. Jain ,  Viraj Y. Sardesai ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

公开(公告)号：US09613956B1

公开(公告)日：2017-04-04

申请号：US15183154

申请日：2016-06-15

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin pitch. Each of the fins has an undoped fin channel and a punchthrough stop doping region underneath the undoped fin channel. A narrow shallow trench isolation trench is formed between the fin pitch of the fins. A wide shallow trench isolation trench is formed at an outside edge of the fins. A doped layer fills the narrow shallow trench isolation trench and the wide shallow trench isolation trench. A vertical thickness of the doped layer in the narrow shallow trench isolation trench is greater than a vertical thickness of the wide shallow trench isolation trench.

公开(公告)号：US09496258B2

公开(公告)日：2016-11-15

申请号：US14510650

申请日：2014-10-09

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

公开(公告)号：US09425196B1

公开(公告)日：2016-08-23

申请号：US14961933

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Fee Li Lie

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/161 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/18 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/161

Abstract: A method of forming a plurality of fins having different threshold voltages from a single semiconductor layer without channel doping. The method may include; forming a first semiconductor having a uniform thickness in an unmerged region, a first merged region, and a second merged region; recessing the first semiconductor in the first and second merged regions, the first semiconductor has a different thickness in each of the unmerged region, the first merged region, and the second merged region; forming a second semiconductor on the first semiconductor in the first and second merged regions; merging the first and second semiconductors to form a first merged semiconductor in the first merged region and a second merged semiconductor in the second merged region; and forming fins in unmerged region, the first merged region, and the second merged region.

Abstract translation: 从没有通道掺杂的单个半导体层形成具有不同阈值电压的多个散热片的方法。 该方法可以包括： 在未熔合区域中形成均匀厚度的第一半导体，第一合并区域和第二合并区域; 在第一和第二合并区域中使第一半导体凹陷，第一半导体在未加工区域，第一合并区域和第二合并区域中的每一个具有不同的厚度; 在第一和第二合并区域中的第一半导体上形成第二半导体; 合并第一和第二半导体以在第一合并区域中形成第一合并半导体，并在第二合并区域中形成第二合并半导体; 在未熔合区域形成翅片，第一合并区域和第二合并区域。

公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US09263449B2

公开(公告)日：2016-02-16

申请号：US14830182

申请日：2015-08-19

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Theodorus E. Standaert

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/00 ,  H01L28/40 ,  H01L28/60 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/8613

Abstract: A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins.

公开(公告)号：US20150380438A1

公开(公告)日：2015-12-31

申请号：US14315362

申请日：2014-06-26

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

公开(公告)号：US09224654B2

公开(公告)日：2015-12-29

申请号：US14088473

申请日：2013-11-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Shom S. Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L27/108 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L21/823431 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/0629 ,  H01L28/90 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor.

Abstract translation: 间隔结构形成在一次性心轴结构的阵列周围并且在掺杂的半导体材料部分之上。 采用侧壁图像转移处理将掺杂半导体材料部分的上部图案化成掺杂半导体鳍片的阵列。 在掺杂半导体鳍片的顶表面和侧壁表面上形成介电材料层之后，形成跨越多个半导体鳍片的门级芯棒结构。 形成导电孔结构以横向围绕多个门级芯棒结构，随后将其移除。 在含导电孔的结构和多个掺杂的半导体鳍片之上形成接触电介质层。 半导体鳍片用作散热片电容器的下电极，并且导电孔结构用作散热片电容器的上电极。

公开(公告)号：US20150364476A1

公开(公告)日：2015-12-17

申请号：US14837349

申请日：2015-08-27

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Pooja R. Batra ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10867 ,  H01L21/743 ,  H01L21/7687 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/66181 ,  H01L29/785 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.