公开(公告)号：US6014330A

公开(公告)日：2000-01-11

申请号：US167969

申请日：1998-10-08

Applicant: Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

Inventor： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Abstract translation: 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5933436A

公开(公告)日：1999-08-03

申请号：US611818

申请日：1996-03-06

Applicant: Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

Inventor： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/15 ,  G11C29/00

CPC classification number: G06F11/1008 ,  H03M13/151

Abstract: An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

Abstract translation: 一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据 。

公开(公告)号：US5774397A

公开(公告)日：1998-06-30

申请号：US711652

申请日：1996-09-10

Applicant: Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

Inventor： Tetsuo Endoh ,  Yoshiyuki Tanaka ,  Seiichi Aritome ,  Riichiro Shirota ,  Susumu Shuto ,  Tomoharu Tanaka ,  Gertjan Hemink ,  Toru Tanzawa

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5621

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Abstract translation: 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和 所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置 栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

公开(公告)号：US5453955A

公开(公告)日：1995-09-26

申请号：US255904

申请日：1994-06-07

Applicant: Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

Inventor： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

IPC: G11C16/02 ,  G11C7/12 ,  G11C16/06 ,  G11C16/26 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C16/26

Abstract: A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

Abstract translation: 非挥发性半导体存储器件包括用于将位线设置在预定读取电位以执行数据读取操作的读取充电晶体管，并且在读取操作期间读取用于将未选择的位线设置为接地电位的放电晶体管。 这些晶体管由不同的控制信号控制，通过根据输入地址对每隔一个位线检测地址变化而获得，使得读出的放电晶体管保持导通，以将未选择的位线设置在地电位之前， 在数据读取操作期间。

公开(公告)号：US5402373A

公开(公告)日：1995-03-28

申请号：US201036

申请日：1994-02-24

Applicant: Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

Inventor： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/0483

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Abstract translation: NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。 每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。 存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。 存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。 在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。 选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

公开(公告)号：US5394372A

公开(公告)日：1995-02-28

申请号：US37585

申请日：1993-03-26

Applicant: Tomoharu Tanaka ,  Riichiro Shirota

Inventor： Tomoharu Tanaka ,  Riichiro Shirota

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: A charge-pump system with an improved oscillation circuit. An electrically programmable non-volatile semiconductor memory device having the charge-pump system with the improved oscillation circuit includes a memory system equipped with a memory circuit having a non-volatile memory function, a oscillating circuit for generating an signal having a frequency which is increased in response to a decrease of a power supply voltage, and a charge-pump circuit which generates a voltage required to write data into or erase data from memory by charge-pumping the power supply voltage according to the signal generated by the oscillating circuit. A ring oscillator serves as the oscillating circuit and the ring oscillator is constituted of a group of inverter circuits connected circularly to one another via a MOS transistor which serves to transfer an electric charge, a gate electrode of the MOS transistor being connected to an output terminal of a voltage converting circuit which increases a transfer capacity of the MOS transistor as the power supply voltage decreases.

Abstract translation: 具有改善振荡电路的电荷泵系统。 具有具有改进的振荡电路的电荷泵系统的电可编程非易失性半导体存储器件包括配备有具有非易失性存储功能的存储电路的存储器系统，用于产生频率增加的信号的振荡电路 响应于电源电压的降低，以及电荷泵电路，其通过根据由振荡电路产生的信号对电源电压进行充电泵浦而产生将数据写入或擦除数据所需的电压。 环形振荡器用作振荡电路，并且环形振荡器由经由用于传送电荷的MOS晶体管彼此圆形连接的一组反相器电路构成，MOS晶体管的栅电极连接到输出端子 的电压转换电路，其随着电源电压降低而增加MOS晶体管的传输容量。

公开(公告)号：US5386422A

公开(公告)日：1995-01-31

申请号：US229761

申请日：1994-04-19

Applicant: Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

Inventor： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

公开(公告)号：US11049942B2

公开(公告)日：2021-06-29

申请号：US16680792

申请日：2019-11-12

Applicant: Te-Chang Tseng ,  Riichiro Shirota

Inventor： Riichiro Shirota ,  Yung-Yueh Chiu ,  Te-Chang Tseng ,  Hiroshi Watanabe

IPC: H01L29/16 ,  H01L29/36 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10

Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

公开(公告)号：US20200168707A1

公开(公告)日：2020-05-28

申请号：US16680792

申请日：2019-11-12

Applicant: TE-CHANG TSENG ,  RIICHIRO SHIROTA

Inventor： RIICHIRO SHIROTA ,  YUNG-YUEH CHIU ,  TE-CHANG TSENG ,  HIROSHI WATANABE

IPC: H01L29/16 ,  H01L29/36 ,  H01L29/10

Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

公开(公告)号：US20170194474A1

公开(公告)日：2017-07-06

申请号：US15390590

申请日：2016-12-26

Applicant: Riichiro Shirota ,  Shinichiro Takatani

Inventor： Riichiro Shirota ,  Shinichiro Takatani

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/51 ,  H01L29/792 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/517 ,  H01L29/7786 ,  H01L29/7831 ,  H01L29/7832 ,  H01L29/788 ,  H01L29/792

Abstract: A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.