公开(公告)号：US07709960B2

公开(公告)日：2010-05-04

申请号：US12186932

申请日：2008-08-06

Applicant: Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

Inventor： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC: H01L23/52

CPC classification number: H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

Abstract translation: Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

公开(公告)号：US07592247B2

公开(公告)日：2009-09-22

申请号：US11538550

申请日：2006-10-04

Applicant: Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

Inventor： Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

IPC: H01L21/4763

CPC classification number: H01L21/76895 ,  B82Y10/00 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1104

Abstract: The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

Abstract translation: 本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构 从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接 其间没有任何金属接触。 可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

公开(公告)号：US20090200674A1

公开(公告)日：2009-08-13

申请号：US12027448

申请日：2008-02-07

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal.

Abstract translation: 描述了形成用于连接线路的两个后端（BEOL）金属布线层的导电通孔的结构和方法。 该方法包括在第一介电层中形成具有第一尺寸宽度的第一互连结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻所述第二介电层中的互连沟槽; 通过使用光刻胶掩模蚀刻互连以形成过渡通孔的第一部分; 使光致抗蚀剂反应至少在横向上扩展光致抗蚀剂; 使用反应的光致抗蚀剂蚀刻所述介电层以形成过渡通孔的第二部分; 以及用金属填充所述互连沟槽和所述互连通孔。

公开(公告)号：US07569434B2

公开(公告)日：2009-08-04

申请号：US11335763

申请日：2006-01-19

Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

IPC: H01L21/00

CPC classification number: H01L29/66742 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

Abstract: In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

Abstract translation: 在第一方面中，提供了在衬底上制造PFET的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。 至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。 此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。 提供了许多其他方面。

公开(公告)号：US07560382B2

公开(公告)日：2009-07-14

申请号：US11467712

申请日：2006-08-28

Applicant: Haining Yang ,  Thomas W. Dyer

Inventor： Haining Yang ,  Thomas W. Dyer

IPC: H01L21/44

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract translation: 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

公开(公告)号：US07531384B2

公开(公告)日：2009-05-12

申请号：US11548298

申请日：2006-10-11

Applicant: Chih-Chao Yang ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： Chih-Chao Yang ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L21/00

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.

Abstract translation: 本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。 互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。 阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

公开(公告)号：US20080290519A1

公开(公告)日：2008-11-27

申请号：US12186932

申请日：2008-08-06

Applicant: Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

Inventor： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC: H01L23/48

CPC classification number: H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

公开(公告)号：US20080224231A1

公开(公告)日：2008-09-18

申请号：US12105298

申请日：2008-04-18

Applicant: Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

IPC: H01L29/76

CPC classification number: H01L29/7834 ,  H01L21/76816 ,  H01L21/84 ,  H01L23/485 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636

Abstract: A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.

Abstract translation: 半导体结构。 半导体结构包括（a）半导体层，（b）栅极电介质区域和（c）栅电极区域。 栅电极区域与半导体层电绝缘。 半导体层包括沟道区，第一和第二源极/漏极区。 沟道区域设置在第一和第二源极/漏极区域之间，并且直接位于栅电极区域下方并与栅电极区域电绝缘。 半导体结构还包括（d）第一和第二导电区域，以及（e）第一和第二接触区域。 第一导电区域和第一源极/漏极区域在第一和第二共同表面处彼此直接物理接触。 第一和第二公共表面不共面。 第一接触区域与第一和第二公共表面重叠。

公开(公告)号：US20080185662A1

公开(公告)日：2008-08-07

申请号：US12062068

申请日：2008-04-03

Applicant: Haining Yang

Inventor： Haining Yang

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

Abstract translation: 用于形成用于半导体器件的非对称间隔结构的方法包括在设置在半导体衬底上的至少一对相邻间隔开的栅极结构上形成间隔层。 栅极结构间隔开，使得间隔层在栅极结构之间的区域中以第一厚度形成，并且在其它位置处形成第二厚度，第二厚度大于所述第一厚度。 蚀刻间隔层以便形成用于一对相邻隔开的栅极结构的非对称间隔结构。

公开(公告)号：US20080164558A1

公开(公告)日：2008-07-10

申请号：US11621124

申请日：2007-01-09

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L23/00 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/3086

Abstract: A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.

Abstract translation: 提供了一种隔离形成在具有绝缘体上硅（SOI）层的半导体衬底上的半导体器件的方法。 该方法包括在沉积在SOI层的表面上的衬垫氮化物层上形成至少一个浅沟槽区，其中至少一个浅沟槽区包括用于暴露SOI层的一部分的开口; 在所述衬垫氮化物层和所述至少一个浅沟槽区域上施加二嵌段共聚物材料; 退火所应用的共聚物材料以形成自组织图案; 并使用二嵌段共聚物材料作为蚀刻掩模部分蚀刻浅沟槽区域。 还描述了半导体结构，其具有形成在半导体衬底的SOI层上的隔离结构，该隔离结构具有氧化的衬底区域; 以及形成在氧化的基板区域上的空隙区域。