公开(公告)号：US20080230868A1

公开(公告)日：2008-09-25

申请号：US12108574

申请日：2008-04-24

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

IPC: H01L29/06

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US20080111162A1

公开(公告)日：2008-05-15

申请号：US11559571

申请日：2006-11-14

Applicant: Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

Inventor： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC: H01L29/04 ,  H01L21/311

CPC classification number: H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract translation: 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

公开(公告)号：US07560382B2

公开(公告)日：2009-07-14

申请号：US11467712

申请日：2006-08-28

Applicant: Haining Yang ,  Thomas W. Dyer

Inventor： Haining Yang ,  Thomas W. Dyer

IPC: H01L21/44

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract translation: 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

公开(公告)号：US20080054313A1

公开(公告)日：2008-03-06

申请号：US11468068

申请日：2006-08-29

Applicant: Thomas W. Dyer ,  Haining Yang

Inventor： Thomas W. Dyer ,  Haining Yang

IPC: H01L29/80

CPC classification number: H01L21/76898 ,  G03F9/7084 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54453 ,  H01L2924/01074 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.

Abstract translation: 本发明涉及具有从衬底的背表面延伸穿过衬底到背面半导体器件的背面接触的器件结构。 基板优选地还包括位于其中的一个或多个对准结构，其中每个在基板的背面处足够可见。 以这种方式，可以使用这种对准结构来进行背面光刻对准，以在衬底的背面上形成图案化抗蚀剂层中的至少一个后接触开口。 形成的后接触开口与前半导体器件光刻对准，并且可以被蚀刻以形成从衬底的背面延伸到前半导体器件上的后接触。 用导电材料填充背面接触孔导致与前半导体器件电接触的导电背接触。

公开(公告)号：US07436030B2

公开(公告)日：2008-10-14

申请号：US11463640

申请日：2006-08-10

Applicant: Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

Inventor： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract translation: 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US20080036012A1

公开(公告)日：2008-02-14

申请号：US11463640

申请日：2006-08-10

Applicant: Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

Inventor： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC: H01L29/76

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract translation: 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US07101744B1

公开(公告)日：2006-09-05

申请号：US10906670

申请日：2005-03-01

Applicant: Thomas W. Dyer ,  Haining Yang

Inventor： Thomas W. Dyer ,  Haining Yang

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Portions of the first type nitride layer and the topographic layer over the second polarity type device are patterned and removed. A second type nitride layer is formed over the second polarity type device, and over remaining portions of the topographic layer over the first polarity type device so as to define a vertical pillar of second type nitride material along a sidewall of the topographic layer, the second type nitride layer in contact with a sidewall of the first type nitride layer. The topographic layer is removed and the vertical pillar is removed.

Abstract translation: 用于形成用于CMOS器件的自对准双氮化硅衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一氮化物层，并在第一氮化物层上形成形貌层。 第一类型氮化物层和第二极性类型器件上的形貌层的部分被图案化和去除。 在第二极性类型器件上形成第二类型氮化物层，并且在第一极性类型器件上方形成地形层的剩余部分，以沿着地形层的侧壁限定第二类型氮化物材料的垂直柱，第二 氮化物层与第一氮化物层的侧壁接触。 去除地形层并移除垂直柱。

公开(公告)号：US07816231B2

公开(公告)日：2010-10-19

申请号：US11468068

申请日：2006-08-29

Applicant: Thomas W. Dyer ,  Haining Yang

Inventor： Thomas W. Dyer ,  Haining Yang

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76898 ,  G03F9/7084 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54453 ,  H01L2924/01074 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.

Abstract translation: 本发明涉及具有从衬底的背表面延伸穿过衬底到背面半导体器件的背面接触的器件结构。 基板优选地还包括位于其中的一个或多个对准结构，其中每个在基板的背面处足够可见。 以这种方式，可以使用这种对准结构来进行背面光刻对准，以在衬底的背面上形成图案化抗蚀剂层中的至少一个后接触开口。 形成的后接触开口与前半导体器件光刻对准，并且可以被蚀刻以形成从衬底的背面延伸到前半导体器件上的后接触。 用导电材料填充背面接触孔导致与前半导体器件电接触的导电背接触。

公开(公告)号：US07808082B2

公开(公告)日：2010-10-05

申请号：US11559571

申请日：2006-11-14

Applicant: Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

Inventor： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC: H01L21/335

CPC classification number: H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract translation: 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

公开(公告)号：US07390745B2

公开(公告)日：2008-06-24

申请号：US11162800

申请日：2005-09-23

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。