公开(公告)号：US09561274B2

公开(公告)日：2017-02-07

申请号：US14123607

申请日：2012-06-07

Applicant: Haining Yang ,  Michele Carbone ,  Marco E. Bianchi

Inventor： Haining Yang ,  Michele Carbone ,  Marco E. Bianchi

IPC: A61K39/395 ,  A61K45/06 ,  A61K49/00 ,  A61K38/17 ,  C07K16/18 ,  C07K16/28 ,  A61K39/00

CPC classification number: A61K39/3955 ,  A61K38/1709 ,  A61K45/06 ,  A61K49/00 ,  A61K2039/505 ,  C07K16/18 ,  C07K16/28 ,  C07K2317/73 ,  C07K2317/76

Abstract: Embodiments provided herewith relate to methods and compositions for treating or preventing cancer. More particularly, several embodiments are drawn to treating or preventing malignant mesothelioma with antagonists of high-mobility group box 1 (HMGB1).

Abstract translation: 本文提供的实施方案涉及用于治疗或预防癌症的方法和组合物。 更具体地，描述了用高迁移率组盒1（HMGB1）的拮抗剂治疗或预防恶性间皮瘤的几个实施方案。

公开(公告)号：US08558320B2

公开(公告)日：2013-10-15

申请号：US12638557

申请日：2009-12-15

Applicant: Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

Inventor： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

IPC: H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

Abstract translation: 一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。 集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。 导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。 导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

公开(公告)号：US08159009B2

公开(公告)日：2012-04-17

申请号：US12621736

申请日：2009-11-19

Applicant: Haining Yang

Inventor： Haining Yang

IPC: H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76224 ,  H01L21/823807 ,  H01L27/112 ,  H01L27/1122 ,  H01L29/78 ,  H01L29/7843 ,  H03K17/687

Abstract: A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.

Abstract translation: 公开了一种具有应变材料的半导体器件。 在特定实施例中，半导体器件包括第一单元，其包括在第一漏极和第一源极之间的第一栅极。 半导体器件还包括与第一单元相邻的第二单元。 第二单元包括在第二漏极和第二源极之间的第二栅极。 半导体器件还包括在第一源极和第二源极之间的浅沟槽隔离区域。 在第一源和第二源上的第一量的应变材料大于在第一漏极和第二漏极上方的第二量的应变材料。

公开(公告)号：US07984408B2

公开(公告)日：2011-07-19

申请号：US11875013

申请日：2007-10-19

Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

IPC: G06F17/50 ,  H01L29/76

CPC classification number: H01L29/78603 ,  G11C29/54 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

Abstract translation: 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

公开(公告)号：US07605081B2

公开(公告)日：2009-10-20

申请号：US11424963

申请日：2006-06-19

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L21/44

CPC classification number: H01L21/31144 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

Abstract: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w

Abstract translation: 提供了一种用于进行子光刻特征图案化的器件结构的方法。 首先，通过在器件结构的上表面上的光刻和蚀刻来形成包含直径d的一个或多个掩模开口的光刻图案掩模层。 接下来，将一层自组装嵌段共聚物施加在光刻图案化的掩模层上，然后退火以在每个掩模开口内形成直径为w的单个单元聚合物嵌段，条件是w

公开(公告)号：US20090186476A1

公开(公告)日：2009-07-23

申请号：US12018440

申请日：2008-01-23

Applicant: Haining Yang ,  Robert C. Wong

Inventor： Haining Yang ,  Robert C. Wong

IPC: H01L21/4763

CPC classification number: H01L27/1104 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203

Abstract: A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.

Abstract translation: 提供了形成改进的静态随机存取存储器（SRAM）互连结构的方法。 该方法包括在形成在半导体衬底的硅层上的图案化多晶硅层的周围形成侧壁隔离物; 去除图案化的多晶硅层以暴露盖层的一部分; 蚀刻盖层的暴露部分以露出硅层的一部分; 蚀刻硅层的一部分，其中所述硅层的一部分将所述SRAM的下拉器件的至少一部分连接到所述SRAM的上拉器件的至少一部分; 形成栅极氧化物; 以及在所述栅极氧化物上形成栅极导体。 还提供互连结构。

公开(公告)号：US20090057780A1

公开(公告)日：2009-03-05

申请号：US11845265

申请日：2007-08-27

Applicant: Robert C. Wong ,  Haining Yang

Inventor： Robert C. Wong ,  Haining Yang

IPC: H01L27/12 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor fin, but not the other of the first semiconductor fin and the second semiconductor fin, the first semiconductor fin and the second semiconductor fin have different channel heights. The semiconductor fins may be used to fabricating a corresponding first finFET and a corresponding second finFET with differing performance characteristics due to the different channel heights of the first semiconductor fin and the second semiconductor fin.

Abstract translation: 半导体结构和制造半导体结构的方法包括在衬底上具有相同整体高度的第一半导体鳍片和第二半导体鳍片。 由于在第一半导体鳍片和第二半导体鳍片之一的基底处存在通道阻挡层而不是第一半导体鳍片和第二半导体鳍片中的另一个，所以第一半导体鳍片和第二半导体鳍片具有 不同渠道高度。 由于第一半导体鳍片和第二半导体鳍片的沟道高度不同，半导体鳍片可以用于制造具有不同性能特性的相应的第一鳍片FET和对应的第二鳍片鳍片。

公开(公告)号：US07479689B2

公开(公告)日：2009-01-20

申请号：US11627384

申请日：2007-01-26

Applicant: Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

Inventor： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

IPC: H01L23/58

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.

Abstract translation: 公开了一种电子可编程保险丝（e-fuse）。 在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

公开(公告)号：US20080230868A1

公开(公告)日：2008-09-25

申请号：US12108574

申请日：2008-04-24

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer ,  James J. Toomey ,  Haining Yang

IPC: H01L29/06

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US20080197499A1

公开(公告)日：2008-08-21

申请号：US11675296

申请日：2007-02-15

Applicant: Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/7684 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

Abstract: An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

Abstract translation: 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。