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公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译： 一个结构。 该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。 第一电极包括第一导电材料。 第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。 第一电介质层包括第一电介质材料和第二电介质材料。 第二电介质层的底表面与第一电介质层的顶表面直接物理接触。 第二电介质层包括第二电介质材料。
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2.发明授权Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。
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公开(公告)号：US07968949B2
公开(公告)日：2011-06-28
申请号：US11668717
申请日：2007-01-30
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译： 公开了触点形成方法和相关的半导体器件。 一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。 结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。
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公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
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公开(公告)号：US20100277210A1
公开(公告)日：2010-11-04
申请号：US12432801
申请日：2009-04-30
IPC分类号： H03L7/06
摘要： a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.
摘要翻译： 中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。 中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。 采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。 可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。
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公开(公告)号：US20100261318A1
公开(公告)日：2010-10-14
申请号：US12822459
申请日：2010-06-24
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/82
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/3011 , H01L2924/00014
摘要： Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
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7.发明授权Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems 失效用于在微电子通信系统中实现增强的手抖动协议的装置公开(公告)号：US07809340B2
公开(公告)日：2010-10-05
申请号：US12127159
申请日：2008-05-27
IPC分类号： H04B1/04
CPC分类号： H04B1/38
摘要： An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common 10 mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the 15 transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译： 提供了一种用于实现用于微电子通信系统的增强的手抖动协议的装置。 发射机和接收机通过传输链路耦合在一起。 发射机接收空闲输入。 当发射机不发送数据并且发射机向接收单元施加第一公共10模式电平时，空闲输入被激活。 当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。 响应于接收机检测共模水平上移，接收器接收发送的数据信号。 在发送所需数据之后，15个发射机终止通信，在空闲输入被激活时降低共模电平。
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8.发明申请Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry 失效自动驱动器/传输线/接收机阻抗匹配电路的设计结构公开(公告)号：US20090115448A1
公开(公告)日：2009-05-07
申请号：US11934825
申请日：2007-11-05
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译： 用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。 阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。 阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以产生与接收器阻抗匹配的输出信号。
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9.发明授权Design structures incorporating interconnect structures with liner repair layers 有权设计结构包括具有衬里修复层的互连结构公开(公告)号：US07494916B2
公开(公告)日：2009-02-24
申请号：US11875345
申请日：2007-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。
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10.发明申请公开(公告)号：US20090007037A1
公开(公告)日：2009-01-01
申请号：US11925413
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/82345 , H01L21/823475 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L28/20 , H01L29/4933 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
摘要翻译： 本发明的实施例一般涉及用于半导体器件的方法，系统和设计结构，更具体地涉及形成部分硅化和完全硅化结构。 制造部分硅化和完全硅化的结构可能涉及创建一个或多个栅极叠层。 可以暴露第一栅极叠层的多晶硅层，并且可以在其上沉积第一金属层以产生部分硅化结构。 此后，可以暴露第二栅极堆叠的多晶硅层，并且可以在其上沉积第二金属层以形成完全硅化的结构。 在一些实施例中，可以不暴露一个或多个栅极叠层的多晶硅层，并且可以用非硅化多晶硅层形成电阻器。
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